From: Krzysztof Kozlowski <krzk@kernel.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Igor Mitsyanko <i.mitsyanko@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Subject: [Qemu-arm] [PATCH v2 4/5] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines
Date: Mon, 13 Mar 2017 20:04:31 +0200 [thread overview]
Message-ID: <20170313180432.7067-5-krzk@kernel.org> (raw)
In-Reply-To: <20170313180432.7067-1-krzk@kernel.org>
Statements under 'case' were in some places wrongly indented bringing
confusion and making the code less readable. Remove also few unneeded
blank lines. No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++-------------------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index cd290637f357..4dd3e441e2e6 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -1015,9 +1015,9 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
- index = GET_G_COMP_IDX(offset);
- shift = 8 * (offset & 0x4);
- value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
+ index = GET_G_COMP_IDX(offset);
+ shift = 8 * (offset & 0x4);
+ value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift);
break;
case G_TCON:
@@ -1066,7 +1066,6 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
lt_i = GET_L_TIMER_IDX(offset);
value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]);
-
break;
case L0_TCON: case L1_TCON:
@@ -1152,23 +1151,23 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
- index = GET_G_COMP_IDX(offset);
- shift = 8 * (offset & 0x4);
- s->g_timer.reg.comp[index] =
- (s->g_timer.reg.comp[index] &
- (((uint64_t)UINT32_MAX << 32) >> shift)) +
- (value << shift);
+ index = GET_G_COMP_IDX(offset);
+ shift = 8 * (offset & 0x4);
+ s->g_timer.reg.comp[index] =
+ (s->g_timer.reg.comp[index] &
+ (((uint64_t)UINT32_MAX << 32) >> shift)) +
+ (value << shift);
- DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
+ DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift);
- if (offset & 0x4) {
- s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
- } else {
- s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
- }
+ if (offset & 0x4) {
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index);
+ } else {
+ s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index);
+ }
- exynos4210_gfrc_restart(s);
- break;
+ exynos4210_gfrc_restart(s);
+ break;
case G_TCON:
old_val = s->g_timer.reg.tcon;
@@ -1206,7 +1205,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
break;
case G_INT_ENB:
-
/* Raise IRQ if transition from disabled to enabled and CSTAT pending */
for (i = 0; i < MCT_GT_CMP_NUM; i++) {
if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon &
@@ -1287,7 +1285,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
break;
case L0_TCNTB: case L1_TCNTB:
-
lt_i = GET_L_TIMER_IDX(offset);
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
@@ -1315,7 +1312,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
break;
case L0_ICNTB: case L1_ICNTB:
-
lt_i = GET_L_TIMER_IDX(offset);
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
@@ -1352,13 +1348,12 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
if (icntb_max[lt_i] < value) {
icntb_max[lt_i] = value;
}
-DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
- lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
+ DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
+ lt_i, value, icntb_max[lt_i], icntb_min[lt_i]);
#endif
-break;
+ break;
case L0_FRCNTB: case L1_FRCNTB:
-
lt_i = GET_L_TIMER_IDX(offset);
index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i);
--
2.9.3
next prev parent reply other threads:[~2017-03-13 18:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-13 18:04 [Qemu-arm] [PATCH v2 0/5] hw: arm: exynos: Bring up secondary CPU + CPUIDLE issue Krzysztof Kozlowski
2017-03-13 18:04 ` [Qemu-arm] [PATCH v2 1/5] hw/intc/exynos4210_gic: Fix GIC memory mappings for secondary CPU Krzysztof Kozlowski
2017-03-13 19:32 ` Philippe Mathieu-Daudé
2017-05-07 10:55 ` Krzysztof Kozlowski
2017-03-13 18:04 ` [Qemu-arm] [PATCH v2 2/5] hw/intc/exynos4210_gic: Use more meaningful name for local variable Krzysztof Kozlowski
2017-03-13 19:30 ` Philippe Mathieu-Daudé
2017-03-13 18:04 ` [Qemu-arm] [PATCH v2 3/5] hw/timer/exynos4210_mct: Fix checkpatch style errors Krzysztof Kozlowski
2017-03-13 19:31 ` Philippe Mathieu-Daudé
2017-03-13 18:04 ` Krzysztof Kozlowski [this message]
2017-03-13 19:32 ` [Qemu-devel] [Qemu-arm] [PATCH v2 4/5] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines Philippe Mathieu-Daudé
2017-03-13 18:04 ` [Qemu-arm] [PATCH v2 5/5] hw/timer/exynos4210_mct: Remove unused defines Krzysztof Kozlowski
2017-03-14 16:55 ` [Qemu-arm] [PATCH v2 0/5] hw: arm: exynos: Bring up secondary CPU + CPUIDLE issue Alex Bennée
2017-03-14 17:35 ` Krzysztof Kozlowski
2017-03-14 18:24 ` Alex Bennée
2017-03-14 18:56 ` Krzysztof Kozlowski
2017-03-15 8:05 ` Alex Bennée
2017-03-15 16:47 ` Krzysztof Kozlowski
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