From: "Alex Bennée" <alex.bennee@linaro.org>
To: richard.henderson@linaro.org
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [RFC PATCH 20/30] softfloat: half-precision compare functions
Date: Fri, 13 Oct 2017 17:24:28 +0100 [thread overview]
Message-ID: <20171013162438.32458-21-alex.bennee@linaro.org> (raw)
In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org>
This is mostly a mechanical conversion of the float32 variants of the
same name with some judicious search/replace and some constants
changed.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 216 ++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++
2 files changed, 224 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index ff967f5525..fdb2999c41 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3884,6 +3884,222 @@ float16 float16_div(float16 a, float16 b, float_status *status)
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. Otherwise, the comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq(float16 a, float16 b, float_status *status)
+{
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ av = float16_val(a);
+ bv = float16_val(b);
+ return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise. The invalid
+| exception is raised if either operand is a NaN. The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. The comparison is performed according
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The invalid exception is raised if either
+| operand is a NaN. The comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 1;
+ }
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. The comparison is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ return ( float16_val(a) == float16_val(b) ) ||
+ ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 );
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than or
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
+| cause an exception. Otherwise, the comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le_quiet(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt_quiet(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The
+| comparison is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 1;
+ }
+ return 0;
+}
+
/* Half precision floats come in two formats: standard IEEE and "ARM" format.
The latter gains extra exponent range by omitting the NaN/Inf encodings. */
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index f1d79b6d03..76a8310780 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -350,6 +350,14 @@ float16 float16_add(float16, float16, float_status *status);
float16 float16_sub(float16, float16, float_status *status);
float16 float16_mul(float16, float16, float_status *status);
float16 float16_div(float16, float16, float_status *status);
+int float16_eq(float16, float16, float_status *status);
+int float16_le(float16, float16, float_status *status);
+int float16_lt(float16, float16, float_status *status);
+int float16_unordered(float16, float16, float_status *status);
+int float16_eq_quiet(float16, float16, float_status *status);
+int float16_le_quiet(float16, float16, float_status *status);
+int float16_lt_quiet(float16, float16, float_status *status);
+int float16_unordered_quiet(float16, float16, float_status *status);
int float16_is_quiet_nan(float16, float_status *status);
int float16_is_signaling_nan(float16, float_status *status);
--
2.14.1
next prev parent reply other threads:[~2017-10-13 16:32 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 16:24 [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
2017-10-13 20:36 ` Richard Henderson
2017-10-14 9:58 ` Laurent Vivier
2017-10-13 16:24 ` [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN Alex Bennée
2017-10-13 20:49 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns Alex Bennée
2017-10-13 20:52 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX Alex Bennée
2017-10-15 16:13 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
2017-10-15 16:14 ` Richard Henderson
2017-10-15 16:54 ` Peter Maydell
2017-10-13 16:24 ` [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2017-10-16 20:10 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix Alex Bennée
2017-10-15 16:28 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode Alex Bennée
2017-10-16 20:16 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing Alex Bennée
2017-10-15 18:02 ` Richard Henderson
2017-10-16 8:20 ` Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support Alex Bennée
2017-10-16 22:01 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) Alex Bennée
2017-10-16 22:08 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX Alex Bennée
2017-10-16 22:24 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc Alex Bennée
2017-10-16 23:47 ` Richard Henderson
2017-10-13 16:24 ` Alex Bennée [this message]
2017-10-17 0:06 ` [RFC PATCH 20/30] softfloat: half-precision compare functions Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) Alex Bennée
2017-10-17 0:36 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same Alex Bennée
2017-10-17 0:39 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) Alex Bennée
2017-10-17 2:17 ` Richard Henderson
2017-10-13 16:24 ` [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 25/30] softfloat: float16_round_to_int Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 28/30] softfloat: float16_to_int16 conversion Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test Alex Bennée
2017-10-13 16:24 ` [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc Alex Bennée
2017-10-13 16:58 ` [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) no-reply
2017-10-13 16:59 ` no-reply
2017-10-17 2:34 ` Richard Henderson
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