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Wed, 21 Mar 2018 15:17:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521645423; bh=9EIgKmg2Boh4iD93w48tiVD8F3YCEGugXtAMVMDFNbQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=QaY+ZNyDd1LQ7ogKZRSiJXi0chVNqKnvuhb91Tu0n7Jxu99dLwV9MDdcQMXiVNpwk CtT7pnQGMP2ESawvLaAEk1oNlnQ7y/r/3trmC2ony6ze/Uh/O50Vav2Z91gca6cl6k 2tQF5oQgUHES9QdP1S+yFYQd5emNfekR+ECpY/ZY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B4DAC60128 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org Date: Wed, 21 Mar 2018 11:17:00 -0400 From: Aaron Lindsay To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Message-ID: <20180321151700.GF24561@codeaurora.org> References: <1521232280-13089-1-git-send-email-alindsay@codeaurora.org> <1521232280-13089-2-git-send-email-alindsay@codeaurora.org> <20180319203509.GD24561@codeaurora.org> <3e12e8ef-e5ee-d690-7d01-c074b6145566@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <3e12e8ef-e5ee-d690-7d01-c074b6145566@amsat.org> User-Agent: Mutt/1.5.23 (2014-03-12) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: Re: [Qemu-arm] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01] X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Michael Spradling , Digant Desai , qemu-devel@nongnu.org, Alistair Francis , qemu-arm@nongnu.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: LDIWEmsoi0EL On Mar 20 02:03, Philippe Mathieu-Daud=E9 wrote: > On 03/19/2018 09:35 PM, Aaron Lindsay wrote: > > On Mar 18 23:35, Philippe Mathieu-Daud=E9 wrote: > >> Hi Aaron, > >> > >> On 03/16/2018 09:30 PM, Aaron Lindsay wrote: > >>> A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]. > >>> pmceid[01] are already being initialized to zero for both A15 and A= 57. > >>> > >>> Signed-off-by: Aaron Lindsay > >>> --- > >>> target/arm/cpu64.c | 2 ++ > >>> 1 file changed, 2 insertions(+) > >>> > >>> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > >>> index 991d764..8c4db31 100644 > >>> --- a/target/arm/cpu64.c > >>> +++ b/target/arm/cpu64.c > >>> @@ -201,6 +201,8 @@ static void aarch64_a53_initfn(Object *obj) > >>> cpu->id_isar5 =3D 0x00011121; > >>> cpu->id_aa64pfr0 =3D 0x00002222; > >>> cpu->id_aa64dfr0 =3D 0x10305106; > >>> + cpu->pmceid0 =3D 0x00000000; > >>> + cpu->pmceid1 =3D 0x00000000; > >>> cpu->id_aa64isar0 =3D 0x00011120; > >>> cpu->id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ > >>> cpu->dbgdidr =3D 0x3516d000; > >>> > >> > >> Maybe we can move this at a single place in arm_cpu_post_init(): > >> > >> if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { > >> cpu->pmceid0 =3D 0x00000000; > >> cpu->pmceid1 =3D 0x00000000; > >> } > >=20 > > I like consolidating the initialization - though I think it can go in > > arm_cpu_realizefn() with the preexisting PMU-related id_aa64dfr0 > > initialization since it is constant once you've chosen a type of > > processor. One of the other patches in this set actually already adds > > some PMCEID initialization there based on PMCR.N. >=20 > Indeed, arm_cpu_realizefn() is a good place. I've consolidated the pmceid[01] initialization into arm_cpu_realizefn() for v4. -Aaron --=20 Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies= , Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.