From: Peter Xu <peterx@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <rth@twiddle.net>,
"Alex Bennée" <alex.bennee@linaro.org>,
"patches@linaro.org" <patches@linaro.org>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Alex Williamson" <alex.williamson@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 14/27] iommu: Add IOMMU index concept to IOMMU API
Date: Wed, 23 May 2018 09:06:36 +0800 [thread overview]
Message-ID: <20180523010636.GC31932@xz-mi> (raw)
In-Reply-To: <CAFEAcA9b6dmpj+B=SO2YsB5sXsh=UPjkjN_U0i-uJhiDn20HHw@mail.gmail.com>
On Tue, May 22, 2018 at 12:11:38PM +0100, Peter Maydell wrote:
> On 22 May 2018 at 12:02, Peter Xu <peterx@redhat.com> wrote:
> > On Tue, May 22, 2018 at 09:40:44AM +0100, Peter Maydell wrote:
> >> On 22 May 2018 at 04:03, Peter Xu <peterx@redhat.com> wrote:
> >> The reason for not just passing in the transaction attributes to
> >> translate is that
> >> (a) the iommu index abstraction makes the notifier setup simpler:
> >> rather than having to have some indication in the API of which
> >> of the transaction attributes are important and which the notifier
> >> cares about, we can just use indexs
> >
> > Hmm, so here IIUC we'll have a new IOMMU notifier that will only
> > listen to part of the IOMMU notifies, e.g., when attrs.secure=true.
> > Yes I think adding something into IOMMUNotifier might work, but just
> > to mention that in IOMMUTLBEntry we have IOMMUTLBEntry.target_as
> > defined. Until now it's hardly used at least on x86 platform since
> > all of the translations on x86 are targeted to the system RAM.
> > However it seems to be quite tailored in this case since it seems to
> > me that different attrs.secure value for translations should be based
> > on different address spaces too. Then in the IOMMU notifiers that
> > would care about MemTxAttrs, could it be possible to identify that by
> > check against the IOMMUTLBEntry.target_as?
>
> No, because you can have a single address space that receives
> transactions with various attributes. (Again, the MPC is an
> example of this.)
>
> >> (b) it means that it's harder to write an iommu with the bug that
> >> it looks at parts of the transaction attributes that it didn't
> >> claim were important in the notifier API
> >
> > It is just confusing to me when I looked at current translate()
> > interface (I copied it from some other patch of the series):
> >
> > @@ -252,9 +252,10 @@ typedef struct IOMMUMemoryRegionClass {
> > * @iommu: the IOMMUMemoryRegion
> > * @hwaddr: address to be translated within the memory region
> > * @flag: requested access permissions
> > + * @iommu_idx: IOMMU index for the translation
> > */
> > IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
> > - IOMMUAccessFlags flag);
> > + IOMMUAccessFlags flag, int iommu_idx);
> >
> > The "iommu_idx" parameter is really hard to understand here at the
> > first glance. Now I think I understand that it is somehow related to
> > the MemTxAttrs, but still it will take time to understand.
>
> The part of the documentation where I try to explain the general
> idea is in this patch, in the comment at the top of the struct:
>
> + * Conceptually an IOMMU provides a mapping from input address
> + * to an output TLB entry. If the IOMMU is aware of memory transaction
> + * attributes and the output TLB entry depends on the transaction
> + * attributes, we represent this using IOMMU indexes. Each index
> + * selects a particular translation table that the IOMMU has:
> + * @attrs_to_index returns the IOMMU index for a set of transaction
> attributes
> + * @translate takes an input address and an IOMMU index
> + * and the mapping returned can only depend on the input address and the
> + * IOMMU index.
> + *
> + * Most IOMMUs don't care about the transaction attributes and support
> + * only a single IOMMU index. A more complex IOMMU might have one index
> + * for secure transactions and one for non-secure transactions.
>
> Do you have suggestions for how to improve on this?
Not yet. But I have some other questions below...
>
> > And if we see current implementation for this (still, I copied code
> > from other patch in the series to here to ease discussion):
> >
> > @@ -498,8 +498,15 @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
> > do {
> > hwaddr addr = *xlat;
> > IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
> > - IOMMUTLBEntry iotlb = imrc->translate(iommu_mr, addr, is_write ?
> > - IOMMU_WO : IOMMU_RO);
> > + int iommu_idx = 0;
> > + IOMMUTLBEntry iotlb;
> > +
> > + if (imrc->attrs_to_index) {
> > + iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
> > + }
> > +
> > + iotlb = imrc->translate(iommu_mr, addr, is_write ?
> > + IOMMU_WO : IOMMU_RO, iommu_idx);
> >
> > Here what if we pass attrs directly into imrc->translate() and just
> > call imrc->attrs_to_index() inside the arch-dependent translate()
> > function? Will that work too?
>
> You don't always have the attributes at the point where you want
> to call translate. (For instance, memory_region_notify_iommu()
> doesn't have attributes.)
>
> I started off with "pass the tx attrs into the translate method",
> which is fine for the code flows which are actually doing
> memory transactions, but breaks down when you try to incorporate
> notifiers.
Could you elaborate a bit more on why IOMMU notifier failed to
corporate when passing in MemTxAttrs? I am not sure I caught the idea
here, but can we copy the MemTxAttrs into IOMMUTLBEntry when
translating, then in IOMMU notifiers we can know the attrs (if that is
what MPC wants)?
>
> > I had a quick glance at the series, I have no thorough idea on the
> > whole stuff, but I'd say some of the patches are exactly what I wanted
> > if to support MemTxAttrs in VT-d emulation one day (now DMAR of VT-d
> > is bypassing MemTxAttrs and IMHO that's incorrect). If we can somehow
> > pass in the MemTxAttrs then that'll be perfect and I can continue to
> > work on that. If we pass in iommu_idx now instead, it would take some
> > time for me to figure out how to further achieve the same goal for
> > VT-d in the future, e.g., I would still want to pass in MemTxAttrs,
> > but that's obviously duplicated with iommu_idx.
>
> The idea is that you should never need to pass in the MemTxAttrs,
> because everything that the IOMMU might care about in the tx attrs
> must be encoded into the iommu index. (The point where the IOMMU
> gets to do that encoding is in its attrs_to_index() method.)
For the DMAR issue I would care about MemTxAttrs.requester_id. Just
to confirm - do you mean I encode the 16bits field into iommu_idx too,
or is there any smarter way to do so? Asked since otherwise iommu_idx
will gradually grow into another MemTxAttrs to me.
Thanks,
--
Peter Xu
next prev parent reply other threads:[~2018-05-23 1:06 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-21 14:03 [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC Peter Maydell
2018-05-21 14:03 ` [PATCH 01/27] memory.h: Improve IOMMU related documentation Peter Maydell
2018-05-21 19:46 ` Richard Henderson
2018-05-22 9:16 ` Alex Bennée
2018-05-22 11:40 ` [Qemu-devel] " Auger Eric
2018-05-21 14:03 ` [PATCH 02/27] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Peter Maydell
2018-05-21 23:54 ` Richard Henderson
2018-05-22 9:21 ` Alex Bennée
2018-05-21 14:03 ` [PATCH 03/27] Make address_space_translate{,_cached}() " Peter Maydell
2018-05-22 10:49 ` Alex Bennée
2018-05-22 16:12 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 04/27] Make address_space_map() " Peter Maydell
2018-05-22 10:49 ` Alex Bennée
2018-05-22 16:13 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 05/27] Make address_space_access_valid() " Peter Maydell
2018-05-22 10:50 ` Alex Bennée
2018-05-22 16:14 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 06/27] Make flatview_extend_translation() " Peter Maydell
2018-05-22 10:56 ` Alex Bennée
2018-05-22 16:15 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 07/27] Make memory_region_access_valid() " Peter Maydell
2018-05-22 10:57 ` Alex Bennée
2018-05-22 16:17 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 08/27] Make MemoryRegion valid.accepts callback " Peter Maydell
2018-05-22 10:58 ` Alex Bennée
2018-05-22 16:20 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 09/27] Make flatview_access_valid() " Peter Maydell
2018-05-22 10:58 ` Alex Bennée
2018-05-22 16:33 ` Richard Henderson
2018-05-22 16:37 ` Peter Maydell
2018-05-21 14:03 ` [PATCH 10/27] Make flatview_translate() " Peter Maydell
2018-05-22 10:58 ` Alex Bennée
2018-05-22 16:33 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 11/27] Make address_space_get_iotlb_entry() " Peter Maydell
2018-05-22 11:00 ` Alex Bennée
2018-05-22 17:29 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 12/27] Make flatview_do_translate() " Peter Maydell
2018-05-22 11:00 ` Alex Bennée
2018-05-22 17:29 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 13/27] Make address_space_translate_iommu " Peter Maydell
2018-05-22 11:00 ` Alex Bennée
2018-05-22 17:30 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 14/27] iommu: Add IOMMU index concept to IOMMU API Peter Maydell
2018-05-22 3:03 ` [Qemu-devel] " Peter Xu
2018-05-22 8:40 ` Peter Maydell
2018-05-22 11:02 ` Peter Xu
2018-05-22 11:11 ` Peter Maydell
2018-05-23 1:06 ` Peter Xu [this message]
2018-05-23 11:47 ` Peter Maydell
2018-05-24 6:23 ` Peter Xu
2018-05-24 10:54 ` Peter Maydell
2018-05-25 2:50 ` Peter Xu
2018-05-25 9:27 ` Auger Eric
2018-05-25 9:34 ` Peter Maydell
2018-05-22 12:58 ` Auger Eric
2018-05-22 13:22 ` Peter Maydell
2018-05-22 14:11 ` Auger Eric
2018-05-22 14:19 ` Peter Maydell
2018-05-22 14:22 ` Auger Eric
2018-05-22 17:42 ` Richard Henderson
2018-05-22 17:51 ` Peter Maydell
2018-05-22 17:52 ` Richard Henderson
2018-05-21 14:03 ` [PATCH 15/27] iommu: Add IOMMU index argument to notifier APIs Peter Maydell
2018-05-22 17:45 ` Richard Henderson
2018-05-23 9:08 ` Alex Bennée
2018-06-04 13:03 ` Peter Maydell
2018-06-04 15:09 ` Alex Bennée
2018-06-04 15:23 ` Peter Maydell
2018-05-24 15:29 ` [Qemu-devel] " Auger Eric
2018-05-24 17:03 ` Peter Maydell
2018-05-24 19:13 ` Auger Eric
2018-05-21 14:03 ` [PATCH 16/27] iommu: Add IOMMU index argument to translate method Peter Maydell
2018-05-22 18:06 ` Richard Henderson
2018-05-23 9:11 ` Alex Bennée
2018-05-21 14:03 ` [PATCH 17/27] exec.c: Handle IOMMUs in address_space_translate_for_iotlb() Peter Maydell
2018-05-23 9:51 ` Alex Bennée
2018-05-23 11:52 ` Peter Maydell
2018-05-24 19:54 ` [Qemu-devel] " Auger Eric
2018-05-25 8:52 ` Peter Maydell
2018-05-25 9:50 ` Auger Eric
2018-05-25 9:59 ` Peter Maydell
2018-05-21 14:03 ` [PATCH 18/27] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller Peter Maydell
2018-05-22 11:30 ` [Qemu-devel] " Auger Eric
2018-05-22 11:56 ` Peter Maydell
2018-05-22 12:23 ` Auger Eric
2018-05-23 10:41 ` Alex Bennée
2018-05-21 14:03 ` [PATCH 19/27] hw/misc/tz-mpc.c: Implement registers Peter Maydell
2018-05-23 10:44 ` Alex Bennée
2018-05-21 14:03 ` [PATCH 20/27] hw/misc/tz-mpc.c: Implement correct blocked-access behaviour Peter Maydell
2018-05-23 10:49 ` Alex Bennée
2018-05-23 11:54 ` Peter Maydell
2018-05-21 14:03 ` [PATCH 21/27] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate Peter Maydell
2018-05-21 14:03 ` [PATCH 22/27] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY Peter Maydell
2018-05-23 11:01 ` Alex Bennée
2018-05-21 14:03 ` [PATCH 23/27] hw/core/or-irq: Support more than 16 inputs to an OR gate Peter Maydell
2018-05-21 14:34 ` Paolo Bonzini
2018-05-21 15:02 ` Peter Maydell
2018-05-30 16:59 ` [Qemu-devel] " Paolo Bonzini
2018-05-30 17:35 ` Peter Maydell
2018-05-31 10:21 ` Paolo Bonzini
2018-05-31 10:50 ` Peter Maydell
2018-05-31 11:50 ` Paolo Bonzini
2018-05-31 11:59 ` Peter Maydell
2018-05-21 14:03 ` [PATCH 24/27] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS Peter Maydell
2018-05-21 14:04 ` [PATCH 25/27] hw/arm/iotkit: Instantiate MPC Peter Maydell
2018-05-23 11:38 ` Alex Bennée
2018-05-21 14:04 ` [PATCH 26/27] hw/arm/iotkit: Wire up MPC interrupt lines Peter Maydell
2018-05-23 11:39 ` Alex Bennée
2018-05-21 14:04 ` [PATCH 27/27] hw/arm/mps2-tz.c: Instantiate MPCs Peter Maydell
2018-05-23 11:41 ` Alex Bennée
2018-05-21 15:10 ` [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC no-reply
2018-05-30 16:58 ` Paolo Bonzini
2018-05-31 9:54 ` Peter Maydell
2018-05-31 13:37 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180523010636.GC31932@xz-mi \
--to=peterx@redhat.com \
--cc=alex.bennee@linaro.org \
--cc=alex.williamson@redhat.com \
--cc=david@gibson.dropbear.id.au \
--cc=patches@linaro.org \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).