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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id k11sm6033876wrx.88.2021.04.16.03.40.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 03:40:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.0?] hw/arm/armsse: Make SSE-300 use Cortex-M55 Date: Fri, 16 Apr 2021 11:40:10 +0100 Message-Id: <20210416104010.13228-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: /tJDApDXHHGd The SSE-300 has a Cortex-M55 (which was the whole reason for us modelling it), but we forgot to actually update the code to let it have a different CPU type from the IoTKit and SSE-200. Add CPU type as a field for ARMSSEInfo instead of hardcoding it to always use a Cortex-M33. Buglink: https://bugs.launchpad.net/qemu/+bug/1923861 Signed-off-by: Peter Maydell --- This is a rather embarrassing bug. None of the test code I ran on the a547 model actually cared about the CPU specifically being an M55... Another one for the "maybe in rc4" bucket. hw/arm/armsse.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 170dea8632d..2e5d0679e7b 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -56,6 +56,7 @@ typedef struct ARMSSEDeviceInfo { struct ARMSSEInfo { const char *name; + const char *cpu_type; uint32_t sse_version; int sram_banks; int num_cpus; @@ -501,6 +502,7 @@ static const ARMSSEInfo armsse_variants[] = { { .name = TYPE_IOTKIT, .sse_version = ARMSSE_IOTKIT, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), .sram_banks = 1, .num_cpus = 1, .sys_version = 0x41743, @@ -519,6 +521,7 @@ static const ARMSSEInfo armsse_variants[] = { { .name = TYPE_SSE200, .sse_version = ARMSSE_SSE200, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), .sram_banks = 4, .num_cpus = 2, .sys_version = 0x22041743, @@ -537,6 +540,7 @@ static const ARMSSEInfo armsse_variants[] = { { .name = TYPE_SSE300, .sse_version = ARMSSE_SSE300, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"), .sram_banks = 2, .num_cpus = 1, .sys_version = 0x7e00043b, @@ -719,8 +723,7 @@ static void armsse_init(Object *obj) name = g_strdup_printf("armv7m%d", i); object_initialize_child(OBJECT(&s->cluster[i]), name, &s->armv7m[i], TYPE_ARMV7M); - qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", - ARM_CPU_TYPE_NAME("cortex-m33")); + qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", info->cpu_type); g_free(name); name = g_strdup_printf("arm-sse-cpu-container%d", i); memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); -- 2.20.1