From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 2002:a19:f807:0:0:0:0:0 with SMTP id a7csp2060165lff; Mon, 14 Jun 2021 08:12:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxcgSBKvhiX5vIgtmNQ5HsR+i1DTjt5sm7D7JcvqAyD4ubEHs0djdn+OO0737p01+3Nys0Q X-Received: by 2002:a05:6402:31a2:: with SMTP id dj2mr17700998edb.206.1623683559760; Mon, 14 Jun 2021 08:12:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623683559; cv=none; d=google.com; s=arc-20160816; b=uO58fYoEVatoq2LXE0CQ+bVuxHUpRQKdVB4opHl310L0JE5yslR07DAZGfyyFdsMVD 2DzrQPzSdAwTEvL1JGIgL/XV9laEALFi0grr5Kx46kbr1Tz/61rHFQv0aXJQh9j2gofl X/73e3SOxlBHAygOHSXStrvIQ9WVmpLB4H2yRt/mtTUi5AJfzsyk7NaEIY1ORhFbONps bgmxe3K1AUsqCKWl1eM0sitTS8HeXiGfUaPsFdndbk/u8Pd2Eimp/wRry7yriHlnZvEB vNSyRwvbJ1lOLh6spk7xV0JCRhSdZv24CN3p4CJMJa599q3IpyOW5RRTyZ6608TiqfmV byOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=/7qixvh89g9/DW4J+NVzZ6nYoyDHZqfP2LcR8cuEH5E=; b=KnkhyaJWd3U3PdGsI2udcWbU7r9sSO5j6a4geYtCtbODzEbV/WSddRpEyepXBp4sdK KcNzduIwaCNSXiIG6MNRDD//29f4ngCHdypIRgjTMvkXIRI09Uo9pEUaWmKbWMUFnLP/ MuQJa+EBPPzBoJSU5QrofU+1EbEF36IPWbMRUvvsQZDP1mKLl3uxbI4vCxDWnEbYvEix h4okODIbVoDeOpslsPajlPTY0iq7Xr8kOEBn1eRL1cmZkqgquJcsviH0dgTVGsPfAXdC U93OusgnsrUw53oi0Q9HOzk6cdGniB2nZ99NJP3Y1e9o0x3v48t0PFDLdRl/vsfFVA1C xFXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GuN1MELU; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ha1si11812689ejb.743.2021.06.14.08.12.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Jun 2021 08:12:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GuN1MELU; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lsoGU-0003XI-N6 for alex.bennee@linaro.org; Mon, 14 Jun 2021 11:12:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lsoEE-000064-Ls for qemu-devel@nongnu.org; Mon, 14 Jun 2021 11:10:19 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:45741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lsoE8-0008WK-SV for qemu-devel@nongnu.org; Mon, 14 Jun 2021 11:10:18 -0400 Received: by mail-wr1-x42a.google.com with SMTP id z8so14939490wrp.12 for ; Mon, 14 Jun 2021 08:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/7qixvh89g9/DW4J+NVzZ6nYoyDHZqfP2LcR8cuEH5E=; b=GuN1MELUrmSPZZKRkvJ1zu6mMDnRJrbfq/+XpkKHRwqxWpneI5Sr0PibJijErXV3sS YgE68I/HuCJ+OZ9zoJAlLmMEJ5fHj0pZfiQRAgAnNMRw2TysYEqZYw+yZ+Gx9GMScDHQ RQuJWV62mQ8Nq6ikEo9kqCJn6vedT6FXDZmvt6fDCdvlcTsip2DsdmzoQjw3yHc79qkK lWsZI6oPzJ87ooUnHU87o5EMso8cqA4hj8luqOXodFDatzlOqAWHNfHqKZj0DkxtVfqY jJqsM6AEClr4VVfDeJFbjuNv1l0o+4nTKBEjvZX7ho/GFU/SnxkS/9Mpo+nOoRMGO3Vb a8mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=/7qixvh89g9/DW4J+NVzZ6nYoyDHZqfP2LcR8cuEH5E=; b=ZwkPMDnmilwGfUfxmGOSwHUiWvKcvDFQ0u8hlG3hL0woYzL7OjZDqmKuOoZSjNoMJQ +M1Zeyl52Pd/CtboK1U4Rahr65ZTQ2M5NsKr7t5tXyEn8G1GNpLsOuV/p40Bk7aCJY07 F16VO09kCbrP0nwrbUz1cuUY8Mlt05IWPSB4jkXHt1EAGaEBzkGqMdWvSp8K8WN8QE4o 3C7cMqJS0dcB3LMo6tkiwouubmj4Fkk8XaCX1ivs2170DdM1sZsyOAafhRNMA85Nup3K NOnBRwo7mmuhRa+CxcWXI0UVZrXsxTaHnf+T1PgjJe2lIfcCPZRjcpM/pyzDsd5xVg+r 4HvQ== X-Gm-Message-State: AOAM5335x5ECQJBdqLQFcS7aNFFJMrNUjMxadyE2L2li84GtQC/IBAp/ kcyYQTMbzlwrTWi8fRHM/P2mbA== X-Received: by 2002:a5d:64ee:: with SMTP id g14mr14942903wri.66.1623683409808; Mon, 14 Jun 2021 08:10:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b8sm20865639wmd.35.2021.06.14.08.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 08:10:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 00/57] target/arm: First slice of MVE implementation Date: Mon, 14 Jun 2021 16:09:10 +0100 Message-Id: <20210614151007.4545-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: NTL7SO6t0dWK This patchseries provides an initial slice of the MVE implementation. (MVE is "vector instructions for M-profile", also known as Helium). The series covers: * framework for MVE decode, including infrastructure for handling predication, PSR.ECI, etc * tail-predication forms of low-overhead-loop insns (LCTP, WLSTP, LETP) * basic (non-gather) loads and stores * pretty much all the integer 2-operand vector and scalar insns * most of the integer 1-operand insns * a handful of other insns but is not (by a long way) complete MVE support, and this code will remain 'dead' until the enable-MVE patch eventually lands. Changes v1->v2: * Addressed code review comments * Where some style changes were suggested and made for patches at the beginning of the series I have retained the r-by tags for later patches which had minor changes to follow that style: - adding 'static const' for function pointer arrays - using mve_check_qreg_bank() - compressing the early-return-false and early-return-true checks in trans functions down to fewer lines - pass only ESIZE, not H, to macros in mve_helper.c - adjustments to handling of QC Patches still in need of review are: 04 "target/arm: Add handling for PSR.ECI/ICI" 07 "target/arm: Implement MVE WLSTP insn" 11 "target/arm: Implement MVE VLDR/VSTR (non-widening forms)" 13 "target/arm: Move expand_pred_b() data to translate.c" (new patch) 14 "target/arm: Implement MVE VCLZ" 17 "target/arm: Implement MVE VREV16, VREV32, VREV64" 19 "target/arm: Implement MVE VABS" 21 "tcg: Make gen_dup_i32() public" (new patch) 22 "target/arm: Implement MVE VDUP" 34 "target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH" 35 "target/arm: Implement MVE VADD (scalar)" 45 "target/arm: Implement MVE VQSHL (vector)" 53 "target/arm: Implement MVE VADC, VSBC" 55 "target/arm: Implement MVE VHCADD" Nobody seemed to object when I posted v1, so I propose to land these via target-arm.next once they pass code review. thanks -- PMM Peter Maydell (57): target/arm: Provide and use H8 and H1_8 macros target/arm: Enable FPSCR.QC bit for MVE target/arm: Handle VPR semantics in existing code target/arm: Add handling for PSR.ECI/ICI target/arm: Let vfp_access_check() handle late NOCP checks target/arm: Implement MVE LCTP target/arm: Implement MVE WLSTP insn target/arm: Implement MVE DLSTP target/arm: Implement MVE LETP insn target/arm: Add framework for MVE decode target/arm: Implement MVE VLDR/VSTR (non-widening forms) target/arm: Implement widening/narrowing MVE VLDR/VSTR insns target/arm: Move expand_pred_b() data to translate.c target/arm: Implement MVE VCLZ target/arm: Implement MVE VCLS bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations target/arm: Implement MVE VREV16, VREV32, VREV64 target/arm: Implement MVE VMVN (register) target/arm: Implement MVE VABS target/arm: Implement MVE VNEG tcg: Make gen_dup_i32() public target/arm: Implement MVE VDUP target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR target/arm: Implement MVE VADD, VSUB, VMUL target/arm: Implement MVE VMULH target/arm: Implement MVE VRMULH target/arm: Implement MVE VMAX, VMIN target/arm: Implement MVE VABD target/arm: Implement MVE VHADD, VHSUB target/arm: Implement MVE VMULL target/arm: Implement MVE VMLALDAV target/arm: Implement MVE VMLSLDAV include/qemu/int128.h: Add function to create Int128 from int64_t target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH target/arm: Implement MVE VADD (scalar) target/arm: Implement MVE VSUB, VMUL (scalar) target/arm: Implement MVE VHADD, VHSUB (scalar) target/arm: Implement MVE VBRSR target/arm: Implement MVE VPST target/arm: Implement MVE VQADD and VQSUB target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) target/arm: Implement MVE VQDMULL scalar target/arm: Implement MVE VQDMULH, VQRDMULH (vector) target/arm: Implement MVE VQADD, VQSUB (vector) target/arm: Implement MVE VQSHL (vector) target/arm: Implement MVE VQRSHL target/arm: Implement MVE VSHL insn target/arm: Implmement MVE VRSHL target/arm: Implement MVE VQDMLADH and VQRDMLADH target/arm: Implement MVE VQDMLSDH and VQRDMLSDH target/arm: Implement MVE VQDMULL (vector) target/arm: Implement MVE VRHADD target/arm: Implement MVE VADC, VSBC target/arm: Implement MVE VCADD target/arm: Implement MVE VHCADD target/arm: Implement MVE VADDV target/arm: Make VMOV scalar <-> gpreg beatwise for MVE include/qemu/bitops.h | 29 + include/qemu/int128.h | 10 + include/tcg/tcg.h | 3 + target/arm/helper-mve.h | 357 ++++++++++ target/arm/helper.h | 2 + target/arm/internals.h | 11 + target/arm/translate-a32.h | 4 + target/arm/translate.h | 19 + target/arm/vec_internal.h | 9 + target/arm/mve.decode | 260 ++++++++ target/arm/t32.decode | 15 +- target/arm/m_helper.c | 54 +- target/arm/mve_helper.c | 1175 +++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 381 ++++------- target/arm/translate-m-nocp.c | 16 +- target/arm/translate-mve.c | 788 ++++++++++++++++++++++ target/arm/translate-vfp.c | 142 +++- target/arm/translate.c | 300 ++++++++- target/arm/vec_helper.c | 116 +++- target/arm/vfp_helper.c | 3 +- tcg/tcg-op-gvec.c | 4 +- target/arm/meson.build | 3 + 22 files changed, 3393 insertions(+), 308 deletions(-) create mode 100644 target/arm/helper-mve.h create mode 100644 target/arm/mve.decode create mode 100644 target/arm/mve_helper.c create mode 100644 target/arm/translate-mve.c -- 2.20.1