* [PATCH v1 04/10] tests/tcg: add memory-sve test for aarch64
[not found] <20220921160801.1490125-1-alex.bennee@linaro.org>
@ 2022-09-21 16:07 ` Alex Bennée
2022-09-28 22:54 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Alex Bennée @ 2022-09-21 16:07 UTC (permalink / raw)
To: qemu-devel
Cc: minyihh, ma.mandourr, Luke.Craig, cota, aaron, kuhn.chenqun,
robhenry, mahmoudabdalghany, Alex Bennée, Peter Maydell,
open list:ARM TCG CPUs
This will be helpful in debugging problems with tracking SVE memory
accesses via the TCG plugins system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Robert Henry <robhenry@microsoft.com>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
---
tests/tcg/aarch64/Makefile.softmmu-target | 7 +++++++
tests/tcg/aarch64/system/boot.S | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
index f6fcd4829e..26701b718c 100644
--- a/tests/tcg/aarch64/Makefile.softmmu-target
+++ b/tests/tcg/aarch64/Makefile.softmmu-target
@@ -31,6 +31,13 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
memory: CFLAGS+=-DCHECK_UNALIGNED=1
+memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
+
+memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3 -fno-tree-loop-distribute-patterns
+
+TESTS+=memory-sve
+
# Running
QEMU_BASE_MACHINE=-M virt -cpu max -display none
QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel
diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S
index e190b1efa6..f136363d2a 100644
--- a/tests/tcg/aarch64/system/boot.S
+++ b/tests/tcg/aarch64/system/boot.S
@@ -179,12 +179,13 @@ __start:
isb
/*
- * Enable FP registers. The standard C pre-amble will be
+ * Enable FP/SVE registers. The standard C pre-amble will be
* saving these and A-profile compilers will use AdvSIMD
* registers unless we tell it not to.
*/
mrs x0, cpacr_el1
orr x0, x0, #(3 << 20)
+ orr x0, x0, #(3 << 16)
msr cpacr_el1, x0
/* Setup some stack space and enter the test code.
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v1 04/10] tests/tcg: add memory-sve test for aarch64
2022-09-21 16:07 ` [PATCH v1 04/10] tests/tcg: add memory-sve test for aarch64 Alex Bennée
@ 2022-09-28 22:54 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2022-09-28 22:54 UTC (permalink / raw)
To: Alex Bennée, qemu-devel
Cc: minyihh, ma.mandourr, Luke.Craig, cota, aaron, kuhn.chenqun,
robhenry, mahmoudabdalghany, Peter Maydell,
open list:ARM TCG CPUs
On 9/21/22 09:07, Alex Bennée wrote:
> This will be helpful in debugging problems with tracking SVE memory
> accesses via the TCG plugins system.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Cc: Robert Henry <robhenry@microsoft.com>
> Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
> ---
> tests/tcg/aarch64/Makefile.softmmu-target | 7 +++++++
> tests/tcg/aarch64/system/boot.S | 3 ++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-09-21 16:07 ` [PATCH v1 04/10] tests/tcg: add memory-sve test for aarch64 Alex Bennée
2022-09-28 22:54 ` Richard Henderson
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