From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v5 7/9] target/arm: Introduce gen_pc_plus_diff for aarch64
Date: Fri, 30 Sep 2022 15:03:10 -0700 [thread overview]
Message-ID: <20220930220312.135327-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org>
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++-----------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 005fd767fb..28a417fb2b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -148,9 +148,14 @@ static void reset_btype(DisasContext *s)
}
}
+static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
+{
+ tcg_gen_movi_i64(dest, s->pc_curr + diff);
+}
+
void gen_a64_update_pc(DisasContext *s, target_long diff)
{
- tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
+ gen_pc_plus_diff(s, cpu_pc, diff);
}
/*
@@ -1368,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
if (insn & (1U << 31)) {
/* BL Branch with link */
- tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
+ gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s));
}
/* B Branch / BL Branch with link */
@@ -2309,11 +2314,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
default:
goto do_unallocated;
}
- gen_a64_set_pc(s, dst);
/* BLR also needs to load return address */
if (opc == 1) {
- tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
+ TCGv_i64 lr = cpu_reg(s, 30);
+ if (dst == lr) {
+ TCGv_i64 tmp = new_tmp_a64(s);
+ tcg_gen_mov_i64(tmp, dst);
+ dst = tmp;
+ }
+ gen_pc_plus_diff(s, lr, curr_insn_len(s));
}
+ gen_a64_set_pc(s, dst);
break;
case 8: /* BRAA */
@@ -2336,11 +2347,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
} else {
dst = cpu_reg(s, rn);
}
- gen_a64_set_pc(s, dst);
/* BLRAA also needs to load return address */
if (opc == 9) {
- tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
+ TCGv_i64 lr = cpu_reg(s, 30);
+ if (dst == lr) {
+ TCGv_i64 tmp = new_tmp_a64(s);
+ tcg_gen_mov_i64(tmp, dst);
+ dst = tmp;
+ }
+ gen_pc_plus_diff(s, lr, curr_insn_len(s));
}
+ gen_a64_set_pc(s, dst);
break;
case 4: /* ERET */
@@ -2908,7 +2925,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
tcg_rt = cpu_reg(s, rt);
- clean_addr = tcg_constant_i64(s->pc_curr + imm);
+ clean_addr = new_tmp_a64(s);
+ gen_pc_plus_diff(s, clean_addr, imm);
if (is_vector) {
do_fp_ld(s, rt, clean_addr, size);
} else {
@@ -4252,23 +4270,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
{
unsigned int page, rd;
- uint64_t base;
- uint64_t offset;
+ int64_t offset;
page = extract32(insn, 31, 1);
/* SignExtend(immhi:immlo) -> offset */
offset = sextract64(insn, 5, 19);
offset = offset << 2 | extract32(insn, 29, 2);
rd = extract32(insn, 0, 5);
- base = s->pc_curr;
if (page) {
/* ADRP (page based) */
- base &= ~0xfff;
offset <<= 12;
+ /* The page offset is ok for TARGET_TB_PCREL. */
+ offset -= s->pc_curr & 0xfff;
}
- tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
+ gen_pc_plus_diff(s, cpu_reg(s, rd), offset);
}
/*
--
2.34.1
next prev parent reply other threads:[~2022-09-30 22:15 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 22:03 [PATCH v5 0/9] target/arm: pc-relative translation blocks Richard Henderson
2022-09-30 22:03 ` [PATCH v5 1/9] target/arm: Introduce curr_insn_len Richard Henderson
2022-09-30 22:03 ` [PATCH v5 2/9] target/arm: Change gen_goto_tb to work on displacements Richard Henderson
2022-09-30 22:03 ` [PATCH v5 3/9] target/arm: Change gen_*set_pc_im to gen_*update_pc Richard Henderson
2022-10-03 14:18 ` Philippe Mathieu-Daudé via
2022-09-30 22:03 ` [PATCH v5 4/9] target/arm: Change gen_exception_insn* to work on displacements Richard Henderson
2022-10-03 14:21 ` Philippe Mathieu-Daudé via
2022-09-30 22:03 ` [PATCH v5 5/9] target/arm: Remove gen_exception_internal_insn pc argument Richard Henderson
2022-10-03 14:22 ` Philippe Mathieu-Daudé via
2022-09-30 22:03 ` [PATCH v5 6/9] target/arm: Change gen_jmp* to work on displacements Richard Henderson
2022-10-04 15:58 ` Peter Maydell
2022-10-04 20:57 ` Richard Henderson
2022-10-05 14:15 ` Peter Maydell
2022-09-30 22:03 ` Richard Henderson [this message]
2022-10-04 16:10 ` [PATCH v5 7/9] target/arm: Introduce gen_pc_plus_diff for aarch64 Peter Maydell
2022-09-30 22:03 ` [PATCH v5 8/9] target/arm: Introduce gen_pc_plus_diff for aarch32 Richard Henderson
2022-10-11 14:51 ` Peter Maydell
2022-10-11 15:52 ` Richard Henderson
2022-09-30 22:03 ` [PATCH v5 9/9] target/arm: Enable TARGET_TB_PCREL Richard Henderson
2022-10-04 16:23 ` Peter Maydell
2022-10-04 19:27 ` Richard Henderson
2022-10-04 21:09 ` Richard Henderson
2022-10-14 17:49 ` Peter Maydell
2022-10-14 19:01 ` Richard Henderson
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