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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e619b46acsm42233765e9.20.2025.10.01.08.06.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 01 Oct 2025 08:06:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Pierrick Bouvier , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/22] target/alpha: Get cpu first addr space with cpu_get_address_space() Date: Wed, 1 Oct 2025 17:05:15 +0200 Message-ID: <20251001150529.14122-11-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251001150529.14122-1-philmd@linaro.org> References: <20251001150529.14122-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org In order to remove the convenient CPUState::as field, access the vcpu first address space using the cpu_get_address_space() helper. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 096eac34458..8819f0b6cb5 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -175,6 +175,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, target_ulong pt, index; int prot = 0; int ret = MM_K_ACV; + AddressSpace *as; /* Handle physical accesses. */ if (mmu_idx == MMU_PHYS_IDX) { @@ -211,6 +212,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* Interpret the page table exactly like PALcode does. */ + as = cpu_get_address_space(cs, 0); pt = env->ptbr; /* TODO: rather than using ldq_phys() to read the page table we should @@ -223,7 +225,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* L1 page table read. */ index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff; - L1pte = ldq_phys(cs->as, pt + index*8); + L1pte = ldq_phys(as, pt + index*8); if (unlikely((L1pte & PTE_VALID) == 0)) { ret = MM_K_TNV; @@ -236,7 +238,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* L2 page table read. */ index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff; - L2pte = ldq_phys(cs->as, pt + index*8); + L2pte = ldq_phys(as, pt + index*8); if (unlikely((L2pte & PTE_VALID) == 0)) { ret = MM_K_TNV; @@ -249,7 +251,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, /* L3 page table read. */ index = (addr >> TARGET_PAGE_BITS) & 0x3ff; - L3pte = ldq_phys(cs->as, pt + index*8); + L3pte = ldq_phys(as, pt + index*8); phys = L3pte >> 32 << TARGET_PAGE_BITS; if (unlikely((L3pte & PTE_VALID) == 0)) { -- 2.51.0