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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e61a0241bsm41643575e9.11.2025.10.01.08.06.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 01 Oct 2025 08:06:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Pierrick Bouvier , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu Subject: [PATCH 13/22] target/i386: Get cpu first addr space with cpu_get_address_space() Date: Wed, 1 Oct 2025 17:05:18 +0200 Message-ID: <20251001150529.14122-14-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251001150529.14122-1-philmd@linaro.org> References: <20251001150529.14122-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org In order to remove the convenient CPUState::as field, access the vcpu first address space using the cpu_get_address_space() helper. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/arch_memory_mapping.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/arch_memory_mapping.c b/target/i386/arch_memory_mapping.c index 560f4689abc..809c4cb0298 100644 --- a/target/i386/arch_memory_mapping.c +++ b/target/i386/arch_memory_mapping.c @@ -273,12 +273,14 @@ bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; int32_t a20_mask; + AddressSpace *as; if (!cpu_paging_enabled(cs)) { /* paging is disabled */ return true; } + as = cpu_get_address_space(cs, 0); a20_mask = x86_get_a20_mask(env); if (env->cr[4] & CR4_PAE_MASK) { #ifdef TARGET_X86_64 @@ -287,12 +289,12 @@ bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, hwaddr pml5e_addr; pml5e_addr = (env->cr[3] & PLM4_ADDR_MASK) & a20_mask; - walk_pml5e(list, cs->as, pml5e_addr, a20_mask); + walk_pml5e(list, as, pml5e_addr, a20_mask); } else { hwaddr pml4e_addr; pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & a20_mask; - walk_pml4e(list, cs->as, pml4e_addr, a20_mask, + walk_pml4e(list, as, pml4e_addr, a20_mask, 0xffffULL << 48); } } else @@ -301,7 +303,7 @@ bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, hwaddr pdpe_addr; pdpe_addr = (env->cr[3] & ~0x1f) & a20_mask; - walk_pdpe2(list, cs->as, pdpe_addr, a20_mask); + walk_pdpe2(list, as, pdpe_addr, a20_mask); } } else { hwaddr pde_addr; @@ -309,7 +311,7 @@ bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, pde_addr = (env->cr[3] & ~0xfff) & a20_mask; pse = !!(env->cr[4] & CR4_PSE_MASK); - walk_pde2(list, cs->as, pde_addr, a20_mask, pse); + walk_pde2(list, as, pde_addr, a20_mask, pse); } return true; -- 2.51.0