From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-riscv@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
qemu-ppc@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Peter Xu" <peterx@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Song Gao" <gaosong@loongson.cn>
Subject: [PATCH 14/22] target/loongarch: Get cpu first addr space with cpu_get_address_space()
Date: Wed, 1 Oct 2025 17:05:19 +0200 [thread overview]
Message-ID: <20251001150529.14122-15-philmd@linaro.org> (raw)
In-Reply-To: <20251001150529.14122-1-philmd@linaro.org>
In order to remove the convenient CPUState::as field, access
the vcpu first address space using the cpu_get_address_space()
helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/loongarch/cpu_helper.c | 5 +++--
target/loongarch/tcg/tlb_helper.c | 7 +++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 4a9db3ea4c1..f2ee66d0d52 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -110,6 +110,7 @@ static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
int access_type, int mmu_idx)
{
CPUState *cs = env_cpu(env);
+ AddressSpace *as = cpu_get_address_space(cs, 0);
target_ulong index, phys;
uint64_t dir_base, dir_width;
uint64_t base;
@@ -134,7 +135,7 @@ static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
/* get next level page directory */
index = (address >> dir_base) & ((1 << dir_width) - 1);
phys = base | index << 3;
- base = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ base = ldq_phys(as, phys) & TARGET_PHYS_MASK;
if (FIELD_EX64(base, TLBENTRY, HUGE)) {
/* base is a huge pte */
break;
@@ -155,7 +156,7 @@ static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
get_dir_base_width(env, &dir_base, &dir_width, 0);
index = (address >> dir_base) & ((1 << dir_width) - 1);
phys = base | index << 3;
- base = ldq_phys(cs->as, phys);
+ base = ldq_phys(as, phys);
}
context->ps = dir_base;
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 8cfce48a297..5173e30b531 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -600,6 +600,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
CPUState *cs = env_cpu(env);
target_ulong badvaddr, index, phys;
uint64_t dir_base, dir_width;
+ AddressSpace *as;
if (unlikely((level == 0) || (level > 4))) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -621,12 +622,13 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
}
}
+ as = cpu_get_address_space(cs, 0);
badvaddr = env->CSR_TLBRBADV;
base = base & TARGET_PHYS_MASK;
get_dir_base_width(env, &dir_base, &dir_width, level);
index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);
phys = base | index << 3;
- return ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ return ldq_phys(as, phys) & TARGET_PHYS_MASK;
}
void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
@@ -680,6 +682,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
return;
}
} else {
+ AddressSpace *as = cpu_get_address_space(cs, 0);
badv = env->CSR_TLBRBADV;
ptindex = (badv >> ptbase) & ((1 << ptwidth) - 1);
@@ -687,7 +690,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
ptoffset0 = ptindex << 3;
ptoffset1 = (ptindex + 1) << 3;
phys = base | (odd ? ptoffset1 : ptoffset0);
- tmp0 = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ tmp0 = ldq_phys(as, phys) & TARGET_PHYS_MASK;
ps = ptbase;
}
--
2.51.0
next prev parent reply other threads:[~2025-10-01 15:20 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 15:05 [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 01/22] system/qtest: Use &address_space_memory for first vCPU address space Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 02/22] disas/disas-mon: Get cpu first addr space with cpu_get_address_space() Philippe Mathieu-Daudé
2025-10-01 15:34 ` BALATON Zoltan
2025-10-01 15:05 ` [PATCH 03/22] monitor/hmp-cmds: " Philippe Mathieu-Daudé
2025-10-01 15:35 ` BALATON Zoltan
2025-10-01 16:23 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 04/22] hw/core/loader: " Philippe Mathieu-Daudé
2025-10-01 15:08 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 05/22] hw/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:23 ` Miles Glenn
2025-10-01 15:05 ` [PATCH 06/22] hw/m86k: " Philippe Mathieu-Daudé
2025-10-18 5:52 ` Thomas Huth
2025-10-01 15:05 ` [PATCH 07/22] target/xtensa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 08/22] target/riscv: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 09/22] semihosting: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 10/22] target/alpha: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 11/22] target/arm: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 12/22] target/hppa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 13/22] target/i386: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` Philippe Mathieu-Daudé [this message]
2025-10-01 15:05 ` [PATCH 15/22] target/m68k: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 16/22] target/microblaze: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 17/22] target/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 18/22] target/s390x: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 19/22] target/sparc: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 20/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 21/22] exec/cpu: Declare cpu_memory_rw_debug() in 'hw/core/cpu.h' and document Philippe Mathieu-Daudé
2025-10-06 19:08 ` Philippe Mathieu-Daudé
2025-10-08 16:25 ` Zhao Liu
2025-10-01 15:05 ` [PATCH 22/22] target/sparc: Reduce inclusions of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2025-10-01 15:39 ` [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field BALATON Zoltan
2025-10-01 16:08 ` Peter Maydell
2025-10-01 16:35 ` Richard Henderson
2025-10-01 16:42 ` Philippe Mathieu-Daudé
2025-10-01 18:38 ` Philippe Mathieu-Daudé
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