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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 31/37] target/arm: Implement TLBIP RVA{L}E3{IS,OS} Date: Tue, 14 Oct 2025 13:07:12 -0700 Message-ID: <20251014200718.422022-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/tlb-insns.c | 53 ++++++++++++++++++++++++++++---------- 1 file changed, 39 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index cbab7f81f9..c7583957b0 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -1073,10 +1073,17 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - do_rvae_write(env, value, vae3_tlbmask(), tlb_force_broadcast(env)); } +static void tlbi_aa64_rvae3_write128(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t vallo, uint64_t valhi) +{ + do_rvae_write128(env, vallo, valhi, vae3_tlbmask(), + tlb_force_broadcast(env)); +} + static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -1087,10 +1094,16 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env, * since we don't support flush-for-specific-ASID-only, * flush-last-level-only or inner/outer specific flushes. */ - do_rvae_write(env, value, vae3_tlbmask(), true); } +static void tlbi_aa64_rvae3is_write128(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t vallo, uint64_t valhi) +{ + do_rvae_write128(env, vallo, valhi, vae3_tlbmask(), true); +} + static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1265,28 +1278,40 @@ static const ARMCPRegInfo tlbirange_reginfo[] = { .write128fn = tlbi_aa64_rvae2_write128 }, { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, - .writefn = tlbi_aa64_rvae3is_write }, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, + .writefn = tlbi_aa64_rvae3is_write, + .write128fn = tlbi_aa64_rvae3is_write128 }, { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, - .writefn = tlbi_aa64_rvae3is_write }, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, + .writefn = tlbi_aa64_rvae3is_write, + .write128fn = tlbi_aa64_rvae3is_write128 }, { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, - .writefn = tlbi_aa64_rvae3is_write }, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, + .writefn = tlbi_aa64_rvae3is_write, + .write128fn = tlbi_aa64_rvae3is_write128 }, { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, - .writefn = tlbi_aa64_rvae3is_write }, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, + .writefn = tlbi_aa64_rvae3is_write, + .write128fn = tlbi_aa64_rvae3is_write128 }, { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, - .writefn = tlbi_aa64_rvae3_write }, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, + .writefn = tlbi_aa64_rvae3_write, + .write128fn = tlbi_aa64_rvae3_write128 }, { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, - .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, - .writefn = tlbi_aa64_rvae3_write }, + .access = PL3_W, + .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, + .writefn = tlbi_aa64_rvae3_write, + .write128fn = tlbi_aa64_rvae3_write128 }, }; static const ARMCPRegInfo tlbios_reginfo[] = { -- 2.43.0