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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Manos Pitsidianakis Subject: [PATCH v2 03/37] target/arm: Update ARMCPRegInfo for 128-bit sysregs Date: Tue, 14 Oct 2025 13:06:44 -0700 Message-ID: <20251014200718.422022-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add ARM_CP_128BIT for type and functions describing 128-bit access. Reviewed-by: Manos Pitsidianakis Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 48a406a5fb..e1d54baead 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -149,6 +149,8 @@ enum { * should not trap to EL2 when HCR_EL2.NV is set. */ ARM_CP_NV_NO_TRAP = 1 << 22, + /* Flag: For ARM_CP_STATE_AA64, sysreg is 128-bit. */ + ARM_CP_128BIT = 1 << 23, }; /* @@ -191,6 +193,10 @@ enum { #define CP_REG_AA32_NS_SHIFT 29 #define CP_REG_AA32_NS_MASK (1 << CP_REG_AA32_NS_SHIFT) +/* Distinguish 64-bit and 128-bit views of AArch64 system registers. */ +#define CP_REG_AA64_128BIT_SHIFT 30 +#define CP_REG_AA64_128BIT_MASK (1 << CP_REG_AA64_128BIT_SHIFT) + /* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ #define CP_REG_AA32_64BIT_SHIFT 15 #define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) @@ -903,6 +909,9 @@ typedef struct ARMCPRegInfo ARMCPRegInfo; typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri); typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); +typedef Int128 CPRead128Fn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPWrite128Fn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t valuelo, uint64_t valuehi); /* Access permission check functions for coprocessor registers. */ typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *ri, @@ -991,6 +1000,11 @@ struct ARMCPRegInfo { * 2. both readfn and writefn are specified */ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + /* + * Offset of the high 64-bits of the field in CPUARMState. + * Similarly, may be omitted if read128fn and write128fn are set. + */ + ptrdiff_t fieldoffsethi; /* * Offsets of the secure and non-secure fields in CPUARMState for the @@ -1046,6 +1060,13 @@ struct ARMCPRegInfo { * fieldoffset is 0 then no reset will be done. */ CPResetFn *resetfn; + + /* For ARM_CP_128BIT, when accessed via MRRS/MSRR. */ + CPAccessFn *access128fn; + CPRead128Fn *read128fn; + CPWrite128Fn *write128fn; + CPRead128Fn *raw_read128fn; + CPWrite128Fn *raw_write128fn; }; void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); @@ -1115,6 +1136,9 @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); */ static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri) { + if (ri->type & ARM_CP_128BIT) { + return MO_128; + } return (ri->state == ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) ? MO_64 : MO_32); } -- 2.43.0