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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 05/37] target/arm: Split add_cpreg_to_hashtable_aa64 Date: Tue, 14 Oct 2025 13:06:46 -0700 Message-ID: <20251014200718.422022-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Rename the existing add_cpreg_to_hashtable_aa64 as *_1. Introduce a new add_cpreg_to_hashtable_aa64 that handles 128-bit and 64-bit views of an AArch64 system register. Signed-off-by: Richard Henderson --- target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3b06704963..c240edf182 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7668,11 +7668,9 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r) } } -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) +static void add_cpreg_to_hashtable_aa64_1(ARMCPU *cpu, ARMCPRegInfo *r, + uint32_t key) { - uint32_t key = ENCODE_AA64_CP_REG(r->opc0, r->opc1, - r->crn, r->crm, r->opc2); - if ((r->type & ARM_CP_ADD_TLBI_NXS) && cpu_isar_feature(aa64_xs, cpu)) { /* @@ -7740,6 +7738,10 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) r2->writefn = NULL; r2->raw_readfn = NULL; r2->raw_writefn = NULL; + r2->read128fn = NULL; + r2->write128fn = NULL; + r2->raw_read128fn = NULL; + r2->raw_write128fn = NULL; r2->accessfn = NULL; r2->fieldoffset = 0; @@ -7761,6 +7763,57 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) ARM_CP_SECSTATE_NS, key); } +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r) +{ + uint32_t key64 = ENCODE_AA64_CP_REG(r->opc0, r->opc1, + r->crn, r->crm, r->opc2); + + /* + * All 128-bit system registers and instructions have 64-bit aliases. + * If the 128-bit feature is enabled, create a duplicate. + */ + if (r->type & ARM_CP_128BIT) { + if (cpu_isar_feature(aa64_sysreg128, cpu) || + cpu_isar_feature(aa64_sysinstr128, cpu)) { + ARMCPRegInfo *r128 = alloc_cpreg(r, NULL); + uint32_t key128 = key64 | CP_REG_AA64_128BIT_MASK; + + r128->accessfn = r128->access128fn; + r128->access128fn = NULL; + r128->readfn = NULL; + r128->writefn = NULL; + r128->raw_readfn = NULL; + r128->raw_writefn = NULL; + + if (r128->vhe_redir_to_el2) { + r128->vhe_redir_to_el2 |= CP_REG_AA64_128BIT_MASK; + } + if (r128->vhe_redir_to_el01) { + r128->vhe_redir_to_el01 |= CP_REG_AA64_128BIT_MASK; + } + + add_cpreg_to_hashtable_aa64_1(cpu, r128, key128); + + /* + * The 128-bit definition is the canonical view. + * The 64-bit definition is an alias, hidden from gdb. + */ + r->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; + } + + /* Squash the original to create the 64-bit view. */ + r->type &= ~ARM_CP_128BIT; + r->access128fn = NULL; + r->read128fn = NULL; + r->write128fn = NULL; + r->raw_read128fn = NULL; + r->raw_write128fn = NULL; + r->fieldoffsethi = 0; + } + + add_cpreg_to_hashtable_aa64_1(cpu, r, key64); +} + void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) { /* -- 2.43.0