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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 07/37] target/arm: Add read_raw_cp_reg128, write_raw_cp_reg128 Date: Tue, 14 Oct 2025 13:06:48 -0700 Message-ID: <20251014200718.422022-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add the functions and update raw_accessors_invalid to match. Add assertions for !ARM_CP_128BIT in read_raw_cp_reg and write_raw_cp_reg. Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/helper.c | 49 +++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 0b0004eff9..f6658abc57 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1157,6 +1157,7 @@ static inline bool cp_access_ok(int current_el, /* Raw read of a coprocessor register (as needed for migration, etc) */ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); +Int128 read_raw_cp_reg128(CPUARMState *env, const ARMCPRegInfo *ri); /* * Return true if the cp register encoding is in the "feature ID space" as diff --git a/target/arm/helper.c b/target/arm/helper.c index e321f404e6..d9d8ae56e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -119,6 +119,7 @@ static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) { + assert(!(ri->type & ARM_CP_128BIT)); /* Raw read of a coprocessor register (as needed for migration, etc). */ if (ri->type & ARM_CP_CONST) { return ri->resetvalue; @@ -134,6 +135,7 @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v) { + assert(!(ri->type & ARM_CP_128BIT)); /* * Raw write of a coprocessor register (as needed for migration, etc). * Note that constant registers are treated as write-ignored; the @@ -151,6 +153,35 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, } } +Int128 read_raw_cp_reg128(CPUARMState *env, const ARMCPRegInfo *ri) +{ + assert(ri->type & ARM_CP_128BIT); + if (ri->raw_read128fn) { + return ri->raw_read128fn(env, ri); + } else if (ri->read128fn) { + return ri->read128fn(env, ri); + } else { + return raw_read128(env, ri); + } +} + +__attribute__((unused)) +static void write_raw_cp_reg128(CPUARMState *env, const ARMCPRegInfo *ri, + Int128 v) +{ + uint64_t lo = int128_getlo(v); + uint64_t hi = int128_gethi(v); + + assert(ri->type & ARM_CP_128BIT); + if (ri->raw_write128fn) { + ri->raw_write128fn(env, ri, lo, hi); + } else if (ri->write128fn) { + ri->write128fn(env, ri, lo, hi); + } else { + raw_write128(env, ri, lo, hi); + } +} + static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { /* @@ -165,12 +196,22 @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri) * The tests here line up with the conditions in read/write_raw_cp_reg() * and assertions in raw_read()/raw_write(). */ - if ((ri->type & ARM_CP_CONST) || - ri->fieldoffset || - ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { + if (ri->type & ARM_CP_CONST) { return false; } - return true; + if (ri->fieldoffset) { + return false; + } + if (ri->type & ARM_CP_128BIT) { + if (ri->fieldoffsethi) { + return false; + } + return !((ri->raw_write128fn || ri->write128fn) && + (ri->raw_read128fn || ri->read128fn)); + } else { + return !((ri->raw_writefn || ri->writefn) && + (ri->raw_readfn || ri->readfn)); + } } bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) -- 2.43.0