* [PATCH v6 01/30] hw/core: Filter machine list available for a particular target binary
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 23:02 ` Pierrick Bouvier
2025-10-20 22:09 ` [PATCH v6 02/30] hw/boards: Move DEFINE_MACHINE() definition closer to its doc string Philippe Mathieu-Daudé
` (28 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Yanan Wang
Binaries can register a QOM type to filter their machines
by filling their TargetInfo::machine_typename field.
Commit 28502121be7 ("system/vl: Filter machine list available
for a particular target binary") added the filter to
machine_help_func() but missed the other places where the machine
list must be filtered, such QMP 'query-machines' command used by
QTests, and select_machine(). Fix that.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/core/machine-qmp-cmds.c | 4 +++-
monitor/qemu-config-qmp.c | 3 ++-
system/vl.c | 3 ++-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 51d5c230f7e..28dfd3e15bd 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -20,6 +20,7 @@
#include "qapi/qobject-input-visitor.h"
#include "qapi/type-helpers.h"
#include "qemu/uuid.h"
+#include "qemu/target-info.h"
#include "qemu/target-info-qapi.h"
#include "qom/qom-qobject.h"
#include "system/hostmem.h"
@@ -94,9 +95,10 @@ CpuInfoFastList *qmp_query_cpus_fast(Error **errp)
MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props,
Error **errp)
{
- GSList *el, *machines = object_class_get_list(TYPE_MACHINE, false);
+ GSList *el, *machines;
MachineInfoList *mach_list = NULL;
+ machines = object_class_get_list(target_machine_typename(), false);
for (el = machines; el; el = el->next) {
MachineClass *mc = el->data;
const char *default_cpu_type = machine_class_default_cpu_type(mc);
diff --git a/monitor/qemu-config-qmp.c b/monitor/qemu-config-qmp.c
index 9a3b183602d..8bd28fc2328 100644
--- a/monitor/qemu-config-qmp.c
+++ b/monitor/qemu-config-qmp.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include "qemu/osdep.h"
+#include "qemu/target-info.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc.h"
#include "qobject/qlist.h"
@@ -128,7 +129,7 @@ static CommandLineParameterInfoList *query_all_machine_properties(void)
ObjectProperty *prop;
bool is_new;
- machines = object_class_get_list(TYPE_MACHINE, false);
+ machines = object_class_get_list(target_machine_typename(), false);
assert(machines);
/* Loop over all machine classes */
diff --git a/system/vl.c b/system/vl.c
index 646239e4a69..a96063f9901 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -1672,7 +1672,8 @@ static MachineClass *select_machine(QDict *qdict, Error **errp)
{
ERRP_GUARD();
const char *machine_type = qdict_get_try_str(qdict, "type");
- g_autoptr(GSList) machines = object_class_get_list(TYPE_MACHINE, false);
+ g_autoptr(GSList) machines = object_class_get_list(target_machine_typename(),
+ false);
MachineClass *machine_class = NULL;
if (machine_type) {
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 01/30] hw/core: Filter machine list available for a particular target binary
2025-10-20 22:09 ` [PATCH v6 01/30] hw/core: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
@ 2025-10-20 23:02 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Paolo Bonzini, Bernhard Beschow,
Peter Maydell, Richard Henderson, Zhao Liu, Eduardo Habkost,
Cédric Le Goater, Marcel Apfelbaum, Yanan Wang
On 2025-10-20 15:09, Philippe Mathieu-Daudé wrote:
> Binaries can register a QOM type to filter their machines
> by filling their TargetInfo::machine_typename field.
>
> Commit 28502121be7 ("system/vl: Filter machine list available
> for a particular target binary") added the filter to
> machine_help_func() but missed the other places where the machine
> list must be filtered, such QMP 'query-machines' command used by
> QTests, and select_machine(). Fix that.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/core/machine-qmp-cmds.c | 4 +++-
> monitor/qemu-config-qmp.c | 3 ++-
> system/vl.c | 3 ++-
> 3 files changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 02/30] hw/boards: Move DEFINE_MACHINE() definition closer to its doc string
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 01/30] hw/core: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 23:02 ` Pierrick Bouvier
2025-10-20 22:09 ` [PATCH v6 03/30] hw/boards: Extend DEFINE_MACHINE macro to cover more use cases Philippe Mathieu-Daudé
` (27 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Yanan Wang
Code movement to have the DEFINE_MACHINE() definition follow
its usage documentation comment.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/boards.h | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 665b6201214..67c94bff1c6 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -503,6 +503,23 @@ struct MachineState {
* DEFINE_VIRT_MACHINE_IMPL(false, major, minor, micro, _, tag)
*/
+#define DEFINE_MACHINE(namestr, machine_initfn) \
+ static void machine_initfn##_class_init(ObjectClass *oc, const void *data) \
+ { \
+ MachineClass *mc = MACHINE_CLASS(oc); \
+ machine_initfn(mc); \
+ } \
+ static const TypeInfo machine_initfn##_typeinfo = { \
+ .name = MACHINE_TYPE_NAME(namestr), \
+ .parent = TYPE_MACHINE, \
+ .class_init = machine_initfn##_class_init, \
+ }; \
+ static void machine_initfn##_register_types(void) \
+ { \
+ type_register_static(&machine_initfn##_typeinfo); \
+ } \
+ type_init(machine_initfn##_register_types)
+
/*
* Helper for dispatching different macros based on how
* many __VA_ARGS__ are passed. Supports 1 to 5 variadic
@@ -762,23 +779,6 @@ struct MachineState {
} \
} while (0)
-#define DEFINE_MACHINE(namestr, machine_initfn) \
- static void machine_initfn##_class_init(ObjectClass *oc, const void *data) \
- { \
- MachineClass *mc = MACHINE_CLASS(oc); \
- machine_initfn(mc); \
- } \
- static const TypeInfo machine_initfn##_typeinfo = { \
- .name = MACHINE_TYPE_NAME(namestr), \
- .parent = TYPE_MACHINE, \
- .class_init = machine_initfn##_class_init, \
- }; \
- static void machine_initfn##_register_types(void) \
- { \
- type_register_static(&machine_initfn##_typeinfo); \
- } \
- type_init(machine_initfn##_register_types)
-
extern GlobalProperty hw_compat_10_1[];
extern const size_t hw_compat_10_1_len;
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 02/30] hw/boards: Move DEFINE_MACHINE() definition closer to its doc string
2025-10-20 22:09 ` [PATCH v6 02/30] hw/boards: Move DEFINE_MACHINE() definition closer to its doc string Philippe Mathieu-Daudé
@ 2025-10-20 23:02 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Paolo Bonzini, Bernhard Beschow,
Peter Maydell, Richard Henderson, Zhao Liu, Eduardo Habkost,
Cédric Le Goater, Marcel Apfelbaum, Yanan Wang
On 2025-10-20 15:09, Philippe Mathieu-Daudé wrote:
> Code movement to have the DEFINE_MACHINE() definition follow
> its usage documentation comment.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/boards.h | 34 +++++++++++++++++-----------------
> 1 file changed, 17 insertions(+), 17 deletions(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 03/30] hw/boards: Extend DEFINE_MACHINE macro to cover more use cases
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 01/30] hw/core: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 02/30] hw/boards: Move DEFINE_MACHINE() definition closer to its doc string Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 23:03 ` Pierrick Bouvier
2025-10-20 22:09 ` [PATCH v6 04/30] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACE_ARRAY() macro Philippe Mathieu-Daudé
` (26 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater, BALATON Zoltan,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Yanan Wang
From: BALATON Zoltan <balaton@eik.bme.hu>
Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler
versions with less parameters based on that. This is inspired by how
the OBJECT_DEFINE macros do this in a similar way to allow using the
shortened definition in more complex cases too.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <d75c8bbed97650f1a4d2d675444582a240a335b4.1760798392.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/boards.h | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 67c94bff1c6..99292edf5a8 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -503,7 +503,8 @@ struct MachineState {
* DEFINE_VIRT_MACHINE_IMPL(false, major, minor, micro, _, tag)
*/
-#define DEFINE_MACHINE(namestr, machine_initfn) \
+#define DEFINE_MACHINE_EXTENDED(namestr, PARENT_NAME, InstanceName, \
+ machine_initfn, ABSTRACT, ...) \
static void machine_initfn##_class_init(ObjectClass *oc, const void *data) \
{ \
MachineClass *mc = MACHINE_CLASS(oc); \
@@ -511,8 +512,11 @@ struct MachineState {
} \
static const TypeInfo machine_initfn##_typeinfo = { \
.name = MACHINE_TYPE_NAME(namestr), \
- .parent = TYPE_MACHINE, \
+ .parent = TYPE_##PARENT_NAME, \
.class_init = machine_initfn##_class_init, \
+ .instance_size = sizeof(InstanceName), \
+ .abstract = ABSTRACT, \
+ .interfaces = (const InterfaceInfo[]) { __VA_ARGS__ }, \
}; \
static void machine_initfn##_register_types(void) \
{ \
@@ -520,6 +524,14 @@ struct MachineState {
} \
type_init(machine_initfn##_register_types)
+#define DEFINE_MACHINE(namestr, machine_initfn) \
+ DEFINE_MACHINE_EXTENDED(namestr, MACHINE, MachineState, machine_initfn, \
+ false, { })
+
+#define DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ...) \
+ DEFINE_MACHINE_EXTENDED(namestr, MACHINE, MachineState, machine_initfn, \
+ false, __VA_ARGS__)
+
/*
* Helper for dispatching different macros based on how
* many __VA_ARGS__ are passed. Supports 1 to 5 variadic
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 03/30] hw/boards: Extend DEFINE_MACHINE macro to cover more use cases
2025-10-20 22:09 ` [PATCH v6 03/30] hw/boards: Extend DEFINE_MACHINE macro to cover more use cases Philippe Mathieu-Daudé
@ 2025-10-20 23:03 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Paolo Bonzini, Bernhard Beschow,
Peter Maydell, Richard Henderson, Zhao Liu, Eduardo Habkost,
Cédric Le Goater, BALATON Zoltan, Marcel Apfelbaum,
Yanan Wang
On 2025-10-20 15:09, Philippe Mathieu-Daudé wrote:
> From: BALATON Zoltan <balaton@eik.bme.hu>
>
> Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler
> versions with less parameters based on that. This is inspired by how
> the OBJECT_DEFINE macros do this in a similar way to allow using the
> shortened definition in more complex cases too.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> Message-ID: <d75c8bbed97650f1a4d2d675444582a240a335b4.1760798392.git.balaton@eik.bme.hu>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/boards.h | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 04/30] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACE_ARRAY() macro
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 03/30] hw/boards: Extend DEFINE_MACHINE macro to cover more use cases Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 05/30] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
` (25 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Yanan Wang
DEFINE_MACHINE_WITH_INTERFACE_ARRAY() is similar to
DEFINE_MACHINE_WITH_INTERFACES() but allows to pass
an InterfaceInfo[] pointer.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/hw/boards.h | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 99292edf5a8..a60e1d83390 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -504,7 +504,7 @@ struct MachineState {
*/
#define DEFINE_MACHINE_EXTENDED(namestr, PARENT_NAME, InstanceName, \
- machine_initfn, ABSTRACT, ...) \
+ machine_initfn, ABSTRACT, ifaces...) \
static void machine_initfn##_class_init(ObjectClass *oc, const void *data) \
{ \
MachineClass *mc = MACHINE_CLASS(oc); \
@@ -516,7 +516,7 @@ struct MachineState {
.class_init = machine_initfn##_class_init, \
.instance_size = sizeof(InstanceName), \
.abstract = ABSTRACT, \
- .interfaces = (const InterfaceInfo[]) { __VA_ARGS__ }, \
+ .interfaces = ifaces, \
}; \
static void machine_initfn##_register_types(void) \
{ \
@@ -526,11 +526,15 @@ struct MachineState {
#define DEFINE_MACHINE(namestr, machine_initfn) \
DEFINE_MACHINE_EXTENDED(namestr, MACHINE, MachineState, machine_initfn, \
- false, { })
+ false, NULL)
+
+#define DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, ifaces...)\
+ DEFINE_MACHINE_EXTENDED(namestr, MACHINE, MachineState, machine_initfn, \
+ false, ifaces)
#define DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ...) \
- DEFINE_MACHINE_EXTENDED(namestr, MACHINE, MachineState, machine_initfn, \
- false, __VA_ARGS__)
+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+ (const InterfaceInfo[]) { __VA_ARGS__ })
/*
* Helper for dispatching different macros based on how
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 05/30] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 04/30] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACE_ARRAY() macro Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 06/30] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
` (24 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Marc-André Lureau,
Daniel P. Berrangé
Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE
QOM interface names to allow machines to implement them.
Register these interfaces in common code in target_info-qom.c used
by all binaries because QOM interfaces must be registered before
being checked (see next commit with the 'none' machine).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 1 +
include/hw/arm/machines-qom.h | 18 ++++++++++++++++++
target-info-qom.c | 24 ++++++++++++++++++++++++
3 files changed, 43 insertions(+)
create mode 100644 include/hw/arm/machines-qom.h
create mode 100644 target-info-qom.c
diff --git a/meson.build b/meson.build
index c5710a6a47c..f4ac0a6e95b 100644
--- a/meson.build
+++ b/meson.build
@@ -3911,6 +3911,7 @@ common_ss.add(pagevary)
specific_ss.add(files('page-vary-target.c'))
common_ss.add(files('target-info.c'))
+system_ss.add(files('target-info-qom.c'))
specific_ss.add(files('target-info-stub.c'))
subdir('backends')
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
new file mode 100644
index 00000000000..a17225f5f92
--- /dev/null
+++ b/include/hw/arm/machines-qom.h
@@ -0,0 +1,18 @@
+/*
+ * QOM type definitions for ARM / Aarch64 machines
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_ARM_MACHINES_QOM_H
+#define HW_ARM_MACHINES_QOM_H
+
+#define TYPE_TARGET_ARM_MACHINE \
+ "target-info-arm-machine"
+
+#define TYPE_TARGET_AARCH64_MACHINE \
+ "target-info-aarch64-machine"
+
+#endif
diff --git a/target-info-qom.c b/target-info-qom.c
new file mode 100644
index 00000000000..7fd58d24818
--- /dev/null
+++ b/target-info-qom.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU binary/target API (QOM types)
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "hw/arm/machines-qom.h"
+
+static const TypeInfo target_info_types[] = {
+ {
+ .name = TYPE_TARGET_ARM_MACHINE,
+ .parent = TYPE_INTERFACE,
+ },
+ {
+ .name = TYPE_TARGET_AARCH64_MACHINE,
+ .parent = TYPE_INTERFACE,
+ },
+};
+
+DEFINE_TYPES(target_info_types)
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 06/30] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 05/30] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 07/30] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
` (23 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Marcel Apfelbaum, Yanan Wang
When we'll start to use target_machine_typename() to filter
machines for the ARM/Aarch64 binaries, the 'none' machine
would be filtered. Register the proper interfaces to keep
it available.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/core/null-machine.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index a6e477a2d88..67b769bd3e0 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -16,6 +16,7 @@
#include "hw/boards.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
+#include "hw/arm/machines-qom.h"
static void machine_none_init(MachineState *mch)
{
@@ -55,4 +56,7 @@ static void machine_none_machine_init(MachineClass *mc)
mc->no_cdrom = 1;
}
-DEFINE_MACHINE("none", machine_none_machine_init)
+DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
+ { TYPE_TARGET_AARCH64_MACHINE },
+ { TYPE_TARGET_ARM_MACHINE },
+ { })
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 07/30] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 06/30] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 22:09 ` [PATCH v6 08/30] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
` (22 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé
A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
will be available on qemu-system-arm and qemu-system-aarch64
binaries.
One defined with DEFINE_MACHINE_AARCH64() will only be available
in the qemu-system-aarch64 binary.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/hw/arm/machines-qom.h | 13 +++++++++++++
target/arm/machine.c | 12 ++++++++++++
2 files changed, 25 insertions(+)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index a17225f5f92..109a8bc4985 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -9,10 +9,23 @@
#ifndef HW_ARM_MACHINES_QOM_H
#define HW_ARM_MACHINES_QOM_H
+#include "hw/boards.h"
+
#define TYPE_TARGET_ARM_MACHINE \
"target-info-arm-machine"
#define TYPE_TARGET_AARCH64_MACHINE \
"target-info-aarch64-machine"
+extern const InterfaceInfo arm_aarch64_machine_interfaces[];
+extern const InterfaceInfo aarch64_machine_interfaces[];
+
+#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+ arm_aarch64_machine_interfaces)
+
+#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
+ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
+ aarch64_machine_interfaces)
+
#endif
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 44a0cf844b0..5c42a82be6c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -9,6 +9,7 @@
#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "target/arm/gtimer.h"
+#include "hw/arm/machines-qom.h"
static bool vfp_needed(void *opaque)
{
@@ -1212,3 +1213,14 @@ const VMStateDescription vmstate_arm_cpu = {
NULL
}
};
+
+const InterfaceInfo arm_aarch64_machine_interfaces[] = {
+ { TYPE_TARGET_ARM_MACHINE },
+ { TYPE_TARGET_AARCH64_MACHINE },
+ { }
+};
+
+const InterfaceInfo aarch64_machine_interfaces[] = {
+ { TYPE_TARGET_AARCH64_MACHINE },
+ { }
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 08/30] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 07/30] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-21 5:41 ` Jan Kiszka
2025-10-20 22:09 ` [PATCH v6 09/30] qemu/target-info: Include missing 'qapi-types-common.h' header Philippe Mathieu-Daudé
` (21 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, Samuel Tardieu, Beniamino Galvani,
Strahinja Jankovic, Antony Pavlov, Igor Mitsyanko, Rob Herring,
Jean-Christophe Dubois, Andrey Smirnov, Subbaraya Sundeep,
Jan Kiszka, Alistair Francis, Tyrone Ting, Hao Wu, Felipe Balbi,
Niek Linnenbank, Radoslaw Biernacki, Leif Lindholm,
Alexandre Iooss, Edgar E. Iglesias
Register machines to be able to run with the qemu-system-arm
and qemu-system-aarch64 binaries, except few machines which
are only available on the qemu-system-aarch64 binary:
$ git grep TARGET_AARCH64 hw/arm/meson.build
hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))
$ git grep -W AARCH64 hw/arm/Kconfig
hw/arm/Kconfig=185=config SBSA_REF
hw/arm/Kconfig-186- bool
hw/arm/Kconfig-187- default y
hw/arm/Kconfig:188: depends on TCG && AARCH64
--
hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM
hw/arm/Kconfig-414- bool
hw/arm/Kconfig-415- default y if PIXMAN
hw/arm/Kconfig:416: depends on TCG && AARCH64
--
hw/arm/Kconfig=435=config XLNX_VERSAL
hw/arm/Kconfig-436- bool
hw/arm/Kconfig-437- default y
hw/arm/Kconfig:438: depends on TCG && AARCH64
--
hw/arm/Kconfig=475=config NPCM8XX
hw/arm/Kconfig-476- bool
hw/arm/Kconfig-477- default y
hw/arm/Kconfig:478: depends on TCG && AARCH64
--
hw/arm/Kconfig=605=config FSL_IMX8MP_EVK
hw/arm/Kconfig-606- bool
hw/arm/Kconfig-607- default y
hw/arm/Kconfig:608: depends on TCG && AARCH64
$ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME
...
hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64
hw/arm/aspeed.c-1940- }, {
hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
hw/arm/raspi.c:420:#ifdef TARGET_AARCH64
hw/arm/raspi.c-421- }, {
hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"),
hw/arm/raspi.c-429- }, {
hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"),
This can be verified as:
$ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help)
@@ -5,3 +4,0 @@
-ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb)
-ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35)
-ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35)
@@ -22 +18,0 @@
-imx8mp-evk NXP i.MX 8M Plus EVK Board
@@ -49 +44,0 @@
-npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35)
@@ -63,3 +57,0 @@
-raspi3ap Raspberry Pi 3A+ (revision 1.0)
-raspi3b Raspberry Pi 3B (revision 1.2)
-raspi4b Raspberry Pi 4B (revision 1.5)
@@ -72 +63,0 @@
-sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine
@@ -116,2 +106,0 @@
-xlnx-versal-virt Xilinx Versal Virtual development board
-xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/arm/aspeed.c | 27 ++++++++++++++++++++++++++-
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/b-l475e-iot01a.c | 2 ++
hw/arm/bananapi_m2u.c | 3 ++-
hw/arm/collie.c | 2 ++
hw/arm/cubieboard.c | 3 ++-
hw/arm/digic_boards.c | 3 ++-
hw/arm/exynos4_boards.c | 3 +++
hw/arm/fby35.c | 2 ++
hw/arm/highbank.c | 3 +++
hw/arm/imx25_pdk.c | 3 ++-
hw/arm/imx8mp-evk.c | 4 +++-
hw/arm/integratorcp.c | 3 ++-
hw/arm/kzm.c | 3 ++-
hw/arm/mcimx6ul-evk.c | 4 +++-
hw/arm/mcimx7d-sabre.c | 4 +++-
hw/arm/microbit.c | 2 ++
hw/arm/mps2-tz.c | 5 +++++
hw/arm/mps2.c | 5 +++++
hw/arm/mps3r.c | 2 ++
hw/arm/msf2-som.c | 3 ++-
hw/arm/musca.c | 3 +++
hw/arm/musicpal.c | 3 ++-
hw/arm/netduino2.c | 3 ++-
hw/arm/netduinoplus2.c | 3 ++-
hw/arm/npcm7xx_boards.c | 6 ++++++
hw/arm/npcm8xx_boards.c | 2 ++
hw/arm/olimex-stm32-h405.c | 3 ++-
hw/arm/omap_sx1.c | 3 +++
hw/arm/orangepi.c | 3 ++-
hw/arm/raspi.c | 6 ++++++
hw/arm/raspi4b.c | 2 ++
hw/arm/realview.c | 5 +++++
hw/arm/sabrelite.c | 3 ++-
hw/arm/sbsa-ref.c | 2 ++
hw/arm/stellaris.c | 3 +++
hw/arm/stm32vldiscovery.c | 3 ++-
hw/arm/versatilepb.c | 3 +++
hw/arm/vexpress.c | 3 +++
hw/arm/virt.c | 2 ++
hw/arm/xilinx_zynq.c | 2 ++
hw/arm/xlnx-versal-virt.c | 3 +++
hw/arm/xlnx-zcu102.c | 2 ++
43 files changed, 138 insertions(+), 18 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 21ee62f7504..0cd76b587f7 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -15,6 +15,7 @@
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_eeprom.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
@@ -1967,99 +1968,123 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_palmetto_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast2500-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2500_evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("romulus-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_romulus_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("sonorapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_sonorapass_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_witherspoon_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_yosemitev2_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("tiogapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_tiogapass_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("g220a-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_g220a_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_qcom_firework_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fp5280g2_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_quanta_q71l_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_rainier_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("fuji-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fuji_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("bletchley-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_bletchley_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_gb200nvl_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("catalina-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_catalina_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("fby35-bmc"),
.parent = MACHINE_TYPE_NAME("ast2600-evb"),
.class_init = aspeed_machine_fby35_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a0_evb_class_init,
- }, {
+ .interfaces = aarch64_machine_interfaces,
+ }, {
.name = MACHINE_TYPE_NAME("ast2700a1-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
+ .interfaces = aarch64_machine_interfaces,
#endif
}, {
.name = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index a61ecff3909..77bc6c4068d 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -22,6 +22,7 @@
#include "hw/arm/boot.h"
#include "hw/block/flash.h"
#include "hw/arm/aspeed_coprocessor.h"
+#include "hw/arm/machines-qom.h"
#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc")
OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC);
@@ -194,6 +195,7 @@ static const TypeInfo ast2700fc_types[] = {
.parent = TYPE_MACHINE,
.class_init = ast2700fc_class_init,
.instance_size = sizeof(Ast2700FCState),
+ .interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 34ed2e0851b..ed275ecce9d 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -29,6 +29,7 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/core/split-irq.h"
+#include "hw/arm/machines-qom.h"
#include "hw/arm/stm32l4x5_soc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "hw/display/dm163.h"
@@ -131,6 +132,7 @@ static const TypeInfo bl475e_machine_type[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(Bl475eMachineState),
.class_init = bl475e_machine_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}
};
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index b750a575f72..90c3ec1c255 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -27,6 +27,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
static struct arm_boot_info bpim2u_binfo;
@@ -144,4 +145,4 @@ static void bpim2u_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("bpim2u", bpim2u_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("bpim2u-pdk", bpim2u_machine_init)
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 93bb190f1f9..ac841ef2b0a 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -15,6 +15,7 @@
#include "hw/boards.h"
#include "strongarm.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/address-spaces.h"
#include "qom/object.h"
@@ -86,6 +87,7 @@ static const TypeInfo collie_machine_typeinfo = {
.parent = TYPE_MACHINE,
.class_init = collie_machine_class_init,
.instance_size = sizeof(CollieMachineState),
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void collie_machine_register_types(void)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index d665d4edd97..c66424effa0 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -22,6 +22,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/i2c/i2c.h"
static struct arm_boot_info cubieboard_binfo = {
@@ -125,4 +126,4 @@ static void cubieboard_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("cubieboard", cubieboard_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("cubieboard", cubieboard_machine_init)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 466b8b84c0e..f71c16be0fe 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -29,6 +29,7 @@
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "hw/arm/digic.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/loader.h"
#include "system/qtest.h"
@@ -145,4 +146,4 @@ static void canon_a1100_machine_init(MachineClass *mc)
mc->default_ram_id = "ram";
}
-DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("canon-a1100", canon_a1100_machine_init)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 73049741312..e39a35df190 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -28,6 +28,7 @@
#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "system/address-spaces.h"
#include "hw/arm/exynos4210.h"
#include "hw/net/lan9118.h"
@@ -172,6 +173,7 @@ static const TypeInfo nuri_type = {
.name = MACHINE_TYPE_NAME("nuri"),
.parent = TYPE_MACHINE,
.class_init = nuri_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void smdkc210_class_init(ObjectClass *oc, const void *data)
@@ -192,6 +194,7 @@ static const TypeInfo smdkc210_type = {
.name = MACHINE_TYPE_NAME("smdkc210"),
.parent = TYPE_MACHINE,
.class_init = smdkc210_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void exynos4_machines_init(void)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index 5a94c847d36..65fb03b6373 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -14,6 +14,7 @@
#include "hw/qdev-clock.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#define TYPE_FBY35 MACHINE_TYPE_NAME("fby35")
OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35);
@@ -194,6 +195,7 @@ static const TypeInfo fby35_types[] = {
.class_init = fby35_class_init,
.instance_size = sizeof(Fby35State),
.instance_init = fby35_instance_init,
+ .interfaces = arm_aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 165c0b741a5..86a64bb4905 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/loader.h"
#include "net/net.h"
#include "system/runstate.h"
@@ -364,6 +365,7 @@ static const TypeInfo highbank_type = {
.name = MACHINE_TYPE_NAME("highbank"),
.parent = TYPE_MACHINE,
.class_init = highbank_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void midway_class_init(ObjectClass *oc, const void *data)
@@ -389,6 +391,7 @@ static const TypeInfo midway_type = {
.name = MACHINE_TYPE_NAME("midway"),
.parent = TYPE_MACHINE,
.class_init = midway_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void calxeda_machines_init(void)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index e95ea5e4e18..87d3c8b91c5 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -28,6 +28,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/fsl-imx25.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "system/qtest.h"
@@ -150,4 +151,4 @@ static void imx25_pdk_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("imx25-pdk", imx25_pdk_machine_init)
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index b3082fa60d8..a40443fb0a7 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -10,6 +10,7 @@
#include "system/address-spaces.h"
#include "hw/arm/boot.h"
#include "hw/arm/fsl-imx8mp.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "system/qtest.h"
@@ -100,4 +101,5 @@ static void imx8mp_evk_machine_init(MachineClass *mc)
mc->max_cpus = FSL_IMX8MP_NUM_CPUS;
mc->default_ram_id = "imx8mp-evk.ram";
}
-DEFINE_MACHINE("imx8mp-evk", imx8mp_evk_machine_init)
+
+DEFINE_MACHINE_AARCH64("imx8mp", imx8mp_evk_machine_init)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index b1d8fbd470a..9e10d0343c7 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -13,6 +13,7 @@
#include "migration/vmstate.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/misc/arm_integrator_debug.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
@@ -693,7 +694,7 @@ static void integratorcp_machine_init(MachineClass *mc)
machine_add_audiodev_property(mc);
}
-DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("integratorcp", integratorcp_machine_init)
static const Property core_properties[] = {
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 362c1454099..1de68b1c5d0 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -17,6 +17,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx31.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "system/address-spaces.h"
@@ -139,4 +140,4 @@ static void kzm_machine_init(MachineClass *mc)
mc->default_ram_id = "kzm.ram";
}
-DEFINE_MACHINE("kzm", kzm_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("kzm", kzm_machine_init)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 86982cb0772..cbc319fa737 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
@@ -76,4 +77,5 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc)
mc->default_ram_id = "mcimx6ul-evk.ram";
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
+
+DEFINE_MACHINE_ARM_AARCH64("mcimx6ul-evk", mcimx6ul_evk_machine_init)
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 33119610113..349924dbb21 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -16,6 +16,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx7.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
@@ -76,4 +77,5 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
mc->default_ram_id = "mcimx7d-sabre.ram";
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)
+
+DEFINE_MACHINE_ARM_AARCH64("mcimx7d-sabre", mcimx7d_sabre_machine_init)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 525443fdb97..41db5715c3f 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -12,6 +12,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "system/system.h"
#include "system/address-spaces.h"
@@ -74,6 +75,7 @@ static const TypeInfo microbit_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(MicrobitMachineState),
.class_init = microbit_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void microbit_machine_init(void)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 5dd87cc0281..2d2637e5d4a 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -52,6 +52,7 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
+#include "hw/arm/machines-qom.h"
#include "hw/or-irq.h"
#include "hw/boards.h"
#include "system/address-spaces.h"
@@ -1463,24 +1464,28 @@ static const TypeInfo mps2tz_an505_info = {
.name = TYPE_MPS2TZ_AN505_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an505_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2tz_an521_info = {
.name = TYPE_MPS2TZ_AN521_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an521_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps3tz_an524_info = {
.name = TYPE_MPS3TZ_AN524_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an524_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps3tz_an547_info = {
.name = TYPE_MPS3TZ_AN547_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an547_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void mps2tz_machine_init(void)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index bd378e360b0..f8d464abadb 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
+#include "hw/arm/machines-qom.h"
#include "hw/or-irq.h"
#include "hw/boards.h"
#include "system/address-spaces.h"
@@ -567,24 +568,28 @@ static const TypeInfo mps2_an385_info = {
.name = TYPE_MPS2_AN385_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an385_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2_an386_info = {
.name = TYPE_MPS2_AN386_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an386_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2_an500_info = {
.name = TYPE_MPS2_AN500_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an500_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2_an511_info = {
.name = TYPE_MPS2_AN511_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an511_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void mps2_machine_init(void)
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 48c73acc62e..683dd97ee09 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -37,6 +37,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/boot.h"
#include "hw/arm/bsa.h"
+#include "hw/arm/machines-qom.h"
#include "hw/char/cmsdk-apb-uart.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/intc/arm_gicv3.h"
@@ -634,6 +635,7 @@ static const TypeInfo mps3r_machine_types[] = {
.name = TYPE_MPS3R_AN536_MACHINE,
.parent = TYPE_MPS3R_MACHINE,
.class_init = mps3r_an536_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 29c76c68605..864b7e56aed 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -32,6 +32,7 @@
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/qdev-clock.h"
#include "system/address-spaces.h"
#include "hw/arm/msf2-soc.h"
@@ -108,4 +109,4 @@ static void emcraft_sf2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("emcraft-sf2", emcraft_sf2_machine_init)
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 250b3b5bf84..64d4f41cd60 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -26,6 +26,7 @@
#include "system/system.h"
#include "hw/arm/boot.h"
#include "hw/arm/armsse.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/char/pl011.h"
#include "hw/core/split-irq.h"
@@ -657,12 +658,14 @@ static const TypeInfo musca_a_info = {
.name = TYPE_MUSCA_A_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_a_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo musca_b1_info = {
.name = TYPE_MUSCA_B1_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_b1_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void musca_machine_init(void)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 329b162eb20..548c218a039 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -15,6 +15,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/boards.h"
@@ -1346,7 +1347,7 @@ static void musicpal_machine_init(MachineClass *mc)
machine_add_audiodev_property(mc);
}
-DEFINE_MACHINE("musicpal", musicpal_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("musicpal", musicpal_machine_init)
static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data)
{
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index df793c77fe1..6b7fee0973f 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -30,6 +30,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (120MHz) */
#define SYSCLK_FRQ 120000000ULL
@@ -65,4 +66,4 @@ static void netduino2_machine_init(MachineClass *mc)
mc->ignore_memory_transaction_failures = true;
}
-DEFINE_MACHINE("netduino2", netduino2_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("netduino2", netduino2_machine_init)
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 81b6334cf72..4a666f226b0 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -30,6 +30,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (168MHz) */
#define SYSCLK_FRQ 168000000ULL
@@ -65,4 +66,4 @@ static void netduinoplus2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("netduinoplus2", netduinoplus2_machine_init)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 465a0e5acec..2bd90847acd 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -17,6 +17,7 @@
#include "qemu/osdep.h"
#include "hw/arm/npcm7xx.h"
+#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
@@ -549,22 +550,27 @@ static const TypeInfo npcm7xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm750-evb"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = npcm750_evb_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-gsj"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gsj_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gbs_bmc_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("kudo-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = kudo_bmc_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("mori-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = mori_bmc_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 3bf3e1f8f16..b179eadef53 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -19,6 +19,7 @@
#include "chardev/char.h"
#include "hw/boards.h"
#include "hw/arm/npcm8xx.h"
+#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/loader.h"
#include "hw/qdev-core.h"
@@ -248,6 +249,7 @@ static const TypeInfo npcm8xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm845-evb"),
.parent = TYPE_NPCM8XX_MACHINE,
.class_init = npcm845_evb_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 1f15620f9fd..4300cfb8862 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
@@ -71,4 +72,4 @@ static void olimex_stm32_h405_machine_init(MachineClass *mc)
mc->default_ram_size = 0;
}
-DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("olimex-stm32-h405", olimex_stm32_h405_machine_init)
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 5d4a31b7aed..aa6b60f0c9e 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -32,6 +32,7 @@
#include "hw/arm/omap.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/qtest.h"
#include "system/address-spaces.h"
@@ -219,6 +220,7 @@ static const TypeInfo sx1_machine_v2_type = {
.name = MACHINE_TYPE_NAME("sx1"),
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v2_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data)
@@ -238,6 +240,7 @@ static const TypeInfo sx1_machine_v1_type = {
.name = MACHINE_TYPE_NAME("sx1-v1"),
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v1_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void sx1_machine_init(void)
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index e0956880d11..3ea78811069 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -26,6 +26,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-h3.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
static struct arm_boot_info orangepi_binfo;
@@ -124,4 +125,4 @@ static void orangepi_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("orangepi-pc", orangepi_machine_init)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 9d9af63d654..ff5d4368e42 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -25,6 +25,7 @@
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
@@ -394,23 +395,28 @@ static const TypeInfo raspi_machine_types[] = {
.name = MACHINE_TYPE_NAME("raspi0"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi0_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
#endif
}, {
.name = TYPE_RASPI_MACHINE,
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 4df951a0d82..0422ae0f00b 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -11,6 +11,7 @@
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
+#include "hw/arm/machines-qom.h"
#include "hw/arm/raspi_platform.h"
#include "hw/display/bcm2835_fb.h"
#include "hw/registerfields.h"
@@ -123,6 +124,7 @@ static const TypeInfo raspi4b_machine_type = {
.parent = TYPE_RASPI_BASE_MACHINE,
.instance_size = sizeof(Raspi4bMachineState),
.class_init = raspi4b_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
};
static void raspi4b_machine_register_type(void)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 5c9050490b4..9deacbd6075 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -13,6 +13,7 @@
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
+#include "hw/arm/machines-qom.h"
#include "hw/core/split-irq.h"
#include "hw/net/lan9118.h"
#include "hw/net/smc91c111.h"
@@ -431,6 +432,7 @@ static const TypeInfo realview_eb_type = {
.name = MACHINE_TYPE_NAME("realview-eb"),
.parent = TYPE_MACHINE,
.class_init = realview_eb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data)
@@ -452,6 +454,7 @@ static const TypeInfo realview_eb_mpcore_type = {
.name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
.parent = TYPE_MACHINE,
.class_init = realview_eb_mpcore_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_pb_a8_class_init(ObjectClass *oc, const void *data)
@@ -471,6 +474,7 @@ static const TypeInfo realview_pb_a8_type = {
.name = MACHINE_TYPE_NAME("realview-pb-a8"),
.parent = TYPE_MACHINE,
.class_init = realview_pb_a8_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data)
@@ -491,6 +495,7 @@ static const TypeInfo realview_pbx_a9_type = {
.name = MACHINE_TYPE_NAME("realview-pbx-a9"),
.parent = TYPE_MACHINE,
.class_init = realview_pbx_a9_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_machine_init(void)
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index df60d47c6fd..91c7467fdc2 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
@@ -113,4 +114,4 @@ static void sabrelite_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("sabrelite", sabrelite_machine_init)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 15c1ff4b140..cf6e6eb208a 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -35,6 +35,7 @@
#include "hw/arm/bsa.h"
#include "hw/arm/fdt.h"
#include "hw/arm/smmuv3.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/ide/ide-bus.h"
@@ -922,6 +923,7 @@ static const TypeInfo sbsa_ref_info = {
.instance_init = sbsa_ref_instance_init,
.class_init = sbsa_ref_class_init,
.instance_size = sizeof(SBSAMachineState),
+ .interfaces = aarch64_machine_interfaces,
};
static void sbsa_ref_machine_init(void)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 031ea3a24e7..9fea3b6e75e 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -15,6 +15,7 @@
#include "hw/sd/sd.h"
#include "hw/ssi/ssi.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "qemu/timer.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
@@ -1427,6 +1428,7 @@ static const TypeInfo lm3s811evb_type = {
.name = MACHINE_TYPE_NAME("lm3s811evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s811evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
/*
@@ -1448,6 +1450,7 @@ static const TypeInfo lm3s6965evb_type = {
.name = MACHINE_TYPE_NAME("lm3s6965evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s6965evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void stellaris_machine_init(void)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index e6c1f5b8d7d..d042bef0bd0 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* stm32vldiscovery implementation is derived from netduinoplus2 */
@@ -68,4 +69,4 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("stm32vldiscovery", stm32vldiscovery_machine_init)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 5cf1a70d10d..8f2a34f8bd9 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -12,6 +12,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
#include "system/system.h"
@@ -431,6 +432,7 @@ static const TypeInfo versatilepb_type = {
.name = MACHINE_TYPE_NAME("versatilepb"),
.parent = TYPE_MACHINE,
.class_init = versatilepb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void versatileab_class_init(ObjectClass *oc, const void *data)
@@ -452,6 +454,7 @@ static const TypeInfo versatileab_type = {
.name = MACHINE_TYPE_NAME("versatileab"),
.parent = TYPE_MACHINE,
.class_init = versatileab_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void versatile_machine_init(void)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 35f8d05ea17..6faecea2635 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -27,6 +27,7 @@
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
+#include "hw/arm/machines-qom.h"
#include "hw/net/lan9118.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
@@ -850,6 +851,7 @@ static const TypeInfo vexpress_a9_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a9_class_init,
.instance_init = vexpress_a9_instance_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo vexpress_a15_info = {
@@ -857,6 +859,7 @@ static const TypeInfo vexpress_a15_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a15_class_init,
.instance_init = vexpress_a15_instance_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void vexpress_machine_init(void)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 175023897a7..20e3f1094cb 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -37,6 +37,7 @@
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
#include "hw/arm/virt.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/display/ramfb.h"
#include "net/net.h"
@@ -127,6 +128,7 @@ static void arm_virt_compat_set(MachineClass *mc)
.name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
.parent = TYPE_VIRT_MACHINE, \
.class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
+ .interfaces = arm_aarch64_machine_interfaces, \
}; \
static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
{ \
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 0372cd0ac46..dd164e1b6a8 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -20,6 +20,7 @@
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/boards.h"
@@ -480,6 +481,7 @@ static const TypeInfo zynq_machine_type = {
.parent = TYPE_MACHINE,
.class_init = zynq_machine_class_init,
.instance_size = sizeof(ZynqMachineState),
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void zynq_machine_register_types(void)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 149b448546e..5e05521a572 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -21,6 +21,7 @@
#include "hw/arm/fdt.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#include "target/arm/cpu.h"
@@ -401,12 +402,14 @@ static const TypeInfo versal_virt_machine_init_typeinfo = {
.name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
.parent = TYPE_XLNX_VERSAL_VIRT_BASE_MACHINE,
.class_init = versal_virt_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
};
static const TypeInfo versal2_virt_machine_init_typeinfo = {
.name = TYPE_XLNX_VERSAL2_VIRT_MACHINE,
.parent = TYPE_XLNX_VERSAL_VIRT_BASE_MACHINE,
.class_init = versal2_virt_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
};
static void versal_virt_machine_init_register_types(void)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 14b6641a713..330f375f63a 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -19,6 +19,7 @@
#include "qapi/error.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
@@ -303,6 +304,7 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
.class_init = xlnx_zcu102_machine_class_init,
.instance_init = xlnx_zcu102_machine_instance_init,
.instance_size = sizeof(XlnxZCU102),
+ .interfaces = aarch64_machine_interfaces,
};
static void xlnx_zcu102_machine_init_register_types(void)
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 08/30] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
2025-10-20 22:09 ` [PATCH v6 08/30] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
@ 2025-10-21 5:41 ` Jan Kiszka
2025-10-21 7:55 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 51+ messages in thread
From: Jan Kiszka @ 2025-10-21 5:41 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, Samuel Tardieu,
Beniamino Galvani, Strahinja Jankovic, Antony Pavlov,
Igor Mitsyanko, Rob Herring, Jean-Christophe Dubois,
Andrey Smirnov, Subbaraya Sundeep, Alistair Francis, Tyrone Ting,
Hao Wu, Felipe Balbi, Niek Linnenbank, Radoslaw Biernacki,
Leif Lindholm, Alexandre Iooss, Edgar E. Iglesias
On 21.10.25 00:09, Philippe Mathieu-Daudé wrote:
> Register machines to be able to run with the qemu-system-arm
> and qemu-system-aarch64 binaries, except few machines which
> are only available on the qemu-system-aarch64 binary:
>
...
> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
> index 329b162eb20..548c218a039 100644
> --- a/hw/arm/musicpal.c
> +++ b/hw/arm/musicpal.c
> @@ -15,6 +15,7 @@
> #include "hw/sysbus.h"
> #include "migration/vmstate.h"
> #include "hw/arm/boot.h"
> +#include "hw/arm/machines-qom.h"
> #include "net/net.h"
> #include "system/system.h"
> #include "hw/boards.h"
> @@ -1346,7 +1347,7 @@ static void musicpal_machine_init(MachineClass *mc)
> machine_add_audiodev_property(mc);
> }
>
> -DEFINE_MACHINE("musicpal", musicpal_machine_init)
> +DEFINE_MACHINE_ARM_AARCH64("musicpal", musicpal_machine_init)
This is modelling a real, ancient device which only had a single CPU
type and runs the original firmware - makes no sense.
Wouldn't be surprised if there are more of this kind in the list.
Jan
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 08/30] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
2025-10-21 5:41 ` Jan Kiszka
@ 2025-10-21 7:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-21 7:55 UTC (permalink / raw)
To: Jan Kiszka, qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, Samuel Tardieu,
Beniamino Galvani, Strahinja Jankovic, Antony Pavlov,
Igor Mitsyanko, Rob Herring, Jean-Christophe Dubois,
Andrey Smirnov, Subbaraya Sundeep, Alistair Francis, Tyrone Ting,
Hao Wu, Felipe Balbi, Niek Linnenbank, Radoslaw Biernacki,
Leif Lindholm, Alexandre Iooss, Edgar E. Iglesias
On 21/10/25 07:41, Jan Kiszka wrote:
> On 21.10.25 00:09, Philippe Mathieu-Daudé wrote:
>> Register machines to be able to run with the qemu-system-arm
>> and qemu-system-aarch64 binaries, except few machines which
>> are only available on the qemu-system-aarch64 binary:
>>
>
> ...
>
>> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
>> index 329b162eb20..548c218a039 100644
>> --- a/hw/arm/musicpal.c
>> +++ b/hw/arm/musicpal.c
>> @@ -15,6 +15,7 @@
>> #include "hw/sysbus.h"
>> #include "migration/vmstate.h"
>> #include "hw/arm/boot.h"
>> +#include "hw/arm/machines-qom.h"
>> #include "net/net.h"
>> #include "system/system.h"
>> #include "hw/boards.h"
>> @@ -1346,7 +1347,7 @@ static void musicpal_machine_init(MachineClass *mc)
>> machine_add_audiodev_property(mc);
>> }
>>
>> -DEFINE_MACHINE("musicpal", musicpal_machine_init)
>> +DEFINE_MACHINE_ARM_AARCH64("musicpal", musicpal_machine_init)
>
> This is modelling a real, ancient device which only had a single CPU
> type and runs the original firmware - makes no sense.
The goal of this effort is to have a single qemu-system-aarch64 binary
absorbing the qemu-system-arm one. At this point we are trying to do
preparatory work with no single change for the users.
Are you suggesting to directly add a DEFINE_MACHINE_ARM() macro for
these 32-bit only machines? This was planned to be done on top, but
maybe you are right, since we have to review this change, better
start with it now...
> Wouldn't be surprised if there are more of this kind in the list.
>
> Jan
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 09/30] qemu/target-info: Include missing 'qapi-types-common.h' header
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 08/30] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 23:04 ` Pierrick Bouvier
2025-10-20 22:09 ` [PATCH v6 10/30] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
` (20 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé
When adding the TargetInfo::@endianness field in commit a37aec2e7d8,
we neglected to include the "qapi-types-common.h" header to get the
EndianMode enum definition. Fix that.
Fixes: a37aec2e7d8 ("qemu/target-info: Add target_endian_mode()")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/qemu/target-info-impl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index 17887f64e26..e446585bf53 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -9,6 +9,7 @@
#ifndef QEMU_TARGET_INFO_IMPL_H
#define QEMU_TARGET_INFO_IMPL_H
+#include "qapi/qapi-types-common.h"
#include "qapi/qapi-types-machine.h"
typedef struct TargetInfo {
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 09/30] qemu/target-info: Include missing 'qapi-types-common.h' header
2025-10-20 22:09 ` [PATCH v6 09/30] qemu/target-info: Include missing 'qapi-types-common.h' header Philippe Mathieu-Daudé
@ 2025-10-20 23:04 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Paolo Bonzini, Bernhard Beschow,
Peter Maydell, Richard Henderson, Zhao Liu, Eduardo Habkost,
Cédric Le Goater
On 2025-10-20 15:09, Philippe Mathieu-Daudé wrote:
> When adding the TargetInfo::@endianness field in commit a37aec2e7d8,
> we neglected to include the "qapi-types-common.h" header to get the
> EndianMode enum definition. Fix that.
>
> Fixes: a37aec2e7d8 ("qemu/target-info: Add target_endian_mode()")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/qemu/target-info-impl.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 10/30] meson: Prepare to accept per-binary TargetInfo structure implementation
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 09/30] qemu/target-info: Include missing 'qapi-types-common.h' header Philippe Mathieu-Daudé
@ 2025-10-20 22:09 ` Philippe Mathieu-Daudé
2025-10-20 22:13 ` [PATCH 11/30] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
` (19 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm, Paolo Bonzini,
Bernhard Beschow, Peter Maydell, Richard Henderson, Zhao Liu,
Eduardo Habkost, Cédric Le Goater,
Philippe Mathieu-Daudé, Marc-André Lureau,
Daniel P. Berrangé
If a file defining the binary TargetInfo structure is available,
link with it. Otherwise keep using the stub.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
MAINTAINERS | 1 +
meson.build | 9 ++++++++-
configs/targets/meson.build | 4 ++++
3 files changed, 13 insertions(+), 1 deletion(-)
create mode 100644 configs/targets/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index 667acd933c7..17f90230bf2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2001,6 +2001,7 @@ M: Philippe Mathieu-Daudé <philmd@linaro.org>
S: Supported
F: include/qemu/target-info*.h
F: target-info*.c
+F: configs/targets/*.c
Xtensa Machines
---------------
diff --git a/meson.build b/meson.build
index f4ac0a6e95b..0f27a2a8f90 100644
--- a/meson.build
+++ b/meson.build
@@ -3312,6 +3312,7 @@ config_devices_h = {}
config_target_h = {}
config_target_mak = {}
config_base_arch_mak = {}
+config_target_info = {}
disassemblers = {
'alpha' : ['CONFIG_ALPHA_DIS'],
@@ -3912,9 +3913,9 @@ specific_ss.add(files('page-vary-target.c'))
common_ss.add(files('target-info.c'))
system_ss.add(files('target-info-qom.c'))
-specific_ss.add(files('target-info-stub.c'))
subdir('backends')
+subdir('configs/targets')
subdir('disas')
subdir('migration')
subdir('monitor')
@@ -4364,6 +4365,12 @@ foreach target : target_dirs
arch_srcs += gdbstub_xml
endif
+ if target in config_target_info
+ arch_srcs += config_target_info[target]
+ else
+ arch_srcs += files('target-info-stub.c')
+ endif
+
t = target_arch[target_base_arch].apply(config_target, strict: false)
arch_srcs += t.sources()
arch_deps += t.dependencies()
diff --git a/configs/targets/meson.build b/configs/targets/meson.build
new file mode 100644
index 00000000000..a9f6b24ec01
--- /dev/null
+++ b/configs/targets/meson.build
@@ -0,0 +1,4 @@
+foreach target : [
+ ]
+ config_target_info += {target : files(target + '.c')}
+endforeach
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 11/30] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64)
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-10-20 22:09 ` [PATCH v6 10/30] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
@ 2025-10-20 22:13 ` Philippe Mathieu-Daudé
2025-10-20 22:13 ` [PATCH 12/30] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
` (18 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:13 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, qemu-arm, Anton Johansson,
Philippe Mathieu-Daudé, Richard Henderson
Implement the TargetInfo structure for qemu-system-arm
and qemu-system-aarch64 binaries.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/targets/aarch64-softmmu.c | 26 ++++++++++++++++++++++++++
configs/targets/arm-softmmu.c | 26 ++++++++++++++++++++++++++
configs/targets/meson.build | 1 +
3 files changed, 53 insertions(+)
create mode 100644 configs/targets/aarch64-softmmu.c
create mode 100644 configs/targets/arm-softmmu.c
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
new file mode 100644
index 00000000000..4e1e2f64da1
--- /dev/null
+++ b/configs/targets/aarch64-softmmu.c
@@ -0,0 +1,26 @@
+/*
+ * QEMU binary/target API (qemu-system-aarch64)
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+#include "hw/arm/machines-qom.h"
+#include "target/arm/cpu-qom.h"
+
+static const TargetInfo target_info_aarch64_system = {
+ .target_name = "aarch64",
+ .target_arch = SYS_EMU_TARGET_AARCH64,
+ .long_bits = 64,
+ .cpu_type = TYPE_ARM_CPU,
+ .machine_typename = TYPE_TARGET_AARCH64_MACHINE,
+ .endianness = ENDIAN_MODE_LITTLE,
+};
+
+const TargetInfo *target_info(void)
+{
+ return &target_info_aarch64_system;
+}
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
new file mode 100644
index 00000000000..9b3fdd2854a
--- /dev/null
+++ b/configs/targets/arm-softmmu.c
@@ -0,0 +1,26 @@
+/*
+ * QEMU binary/target API (qemu-system-arm)
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+#include "hw/arm/machines-qom.h"
+#include "target/arm/cpu-qom.h"
+
+static const TargetInfo target_info_arm_system = {
+ .target_name = "arm",
+ .target_arch = SYS_EMU_TARGET_ARM,
+ .long_bits = 32,
+ .cpu_type = TYPE_ARM_CPU,
+ .machine_typename = TYPE_TARGET_ARM_MACHINE,
+ .endianness = ENDIAN_MODE_LITTLE,
+};
+
+const TargetInfo *target_info(void)
+{
+ return &target_info_arm_system;
+}
diff --git a/configs/targets/meson.build b/configs/targets/meson.build
index a9f6b24ec01..cca2514eb51 100644
--- a/configs/targets/meson.build
+++ b/configs/targets/meson.build
@@ -1,4 +1,5 @@
foreach target : [
+ 'arm-softmmu', 'aarch64-softmmu',
]
config_target_info += {target : files(target + '.c')}
endforeach
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 12/30] hw/arm/aspeed: Build objects once
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2025-10-20 22:13 ` [PATCH 11/30] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
@ 2025-10-20 22:13 ` Philippe Mathieu-Daudé
2025-10-20 22:13 ` [PATCH 13/30] hw/arm/raspi: " Philippe Mathieu-Daudé
` (17 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:13 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, qemu-arm, Anton Johansson,
Philippe Mathieu-Daudé, Richard Henderson,
Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley
Now than Aspeed machines can be filtered when running a
qemu-system-arm or qemu-system-aarch64 binary, we can
remove the TARGET_AARCH64 #ifdef'ry and compile the
aspeed.c file once, moving it from arm_ss[] source set
to arm_common_ss[].
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/aspeed.c | 6 ------
hw/arm/meson.build | 9 ++++-----
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 0cd76b587f7..d1a746e3b0b 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -180,13 +180,11 @@ struct AspeedMachineState {
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
-#ifdef TARGET_AARCH64
/* AST2700 evb hardware value */
/* SCU HW Strap1 */
#define AST2700_EVB_HW_STRAP1 0x00000800
/* SCUIO HW Strap1 */
#define AST2700_EVB_HW_STRAP2 0x00000700
-#endif
/* Rainier hardware value: (QEMU prototype) */
#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
@@ -1869,7 +1867,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
aspeed_machine_class_init_cpus_defaults(mc);
}
-#ifdef TARGET_AARCH64
static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = bmc->soc;
@@ -1921,7 +1918,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
-#endif
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
const void *data)
@@ -2074,7 +2070,6 @@ static const TypeInfo aspeed_machine_types[] = {
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
.interfaces = arm_aarch64_machine_interfaces,
-#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent = TYPE_ASPEED_MACHINE,
@@ -2085,7 +2080,6 @@ static const TypeInfo aspeed_machine_types[] = {
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
.interfaces = aarch64_machine_interfaces,
-#endif
}, {
.name = TYPE_ASPEED_MACHINE,
.parent = TYPE_MACHINE,
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index b88b5b06d7e..98783bbbdeb 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -40,20 +40,19 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x
arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
-arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed.c',
'aspeed_soc_common.c',
+ 'aspeed_coprocessor_common.c',
'aspeed_ast2400.c',
'aspeed_ast2600.c',
'aspeed_ast10x0.c',
- 'aspeed_eeprom.c',
- 'fby35.c'))
-arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
'aspeed_ast27x0-fc.c',
'aspeed_ast27x0-ssp.c',
'aspeed_ast27x0-tsp.c',
- 'aspeed_coprocessor_common.c'))
+ 'aspeed_eeprom.c',
+ 'fby35.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 13/30] hw/arm/raspi: Build objects once
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2025-10-20 22:13 ` [PATCH 12/30] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
@ 2025-10-20 22:13 ` Philippe Mathieu-Daudé
2025-10-20 22:13 ` [PATCH 14/30] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
` (16 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:13 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, qemu-arm, Anton Johansson,
Philippe Mathieu-Daudé, Richard Henderson, Peter Maydell
Now than Raspi machines can be filtered when running a
qemu-system-arm or qemu-system-aarch64 binary, we can
remove the TARGET_AARCH64 #ifdef'ry and compile the
aspeed.c file once, moving it from arm_ss[] source set
to arm_common_ss[]. Note, we expose the TYPE_BCM2837
and TYPE_BCM2838 types to qemu-system-arm, but they are
not user-creatable, so not an issue.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/bcm2836.c | 4 ----
hw/arm/raspi.c | 4 ----
hw/arm/meson.build | 8 ++++++--
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index cd61ba15054..aaaff05624c 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -195,7 +195,6 @@ static void bcm2836_class_init(ObjectClass *oc, const void *data)
dc->realize = bcm2836_realize;
};
-#ifdef TARGET_AARCH64
static void bcm2837_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -208,7 +207,6 @@ static void bcm2837_class_init(ObjectClass *oc, const void *data)
bc->clusterid = 0x0;
dc->realize = bcm2836_realize;
};
-#endif
static const TypeInfo bcm283x_types[] = {
{
@@ -219,12 +217,10 @@ static const TypeInfo bcm283x_types[] = {
.name = TYPE_BCM2836,
.parent = TYPE_BCM283X,
.class_init = bcm2836_class_init,
-#ifdef TARGET_AARCH64
}, {
.name = TYPE_BCM2837,
.parent = TYPE_BCM283X,
.class_init = bcm2837_class_init,
-#endif
}, {
.name = TYPE_BCM283X,
.parent = TYPE_BCM283X_BASE,
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index ff5d4368e42..bc9e2b4b361 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -368,7 +368,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, const void *data)
raspi_machine_class_init(mc, rmc->board_rev);
};
-#ifdef TARGET_AARCH64
static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -388,7 +387,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, const void *data)
rmc->board_rev = 0xa02082;
raspi_machine_class_init(mc, rmc->board_rev);
};
-#endif /* TARGET_AARCH64 */
static const TypeInfo raspi_machine_types[] = {
{
@@ -406,7 +404,6 @@ static const TypeInfo raspi_machine_types[] = {
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
.interfaces = arm_aarch64_machine_interfaces,
-#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
@@ -417,7 +414,6 @@ static const TypeInfo raspi_machine_types[] = {
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
.interfaces = aarch64_machine_interfaces,
-#endif
}, {
.name = TYPE_RASPI_MACHINE,
.parent = TYPE_RASPI_BASE_MACHINE,
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 98783bbbdeb..a12d690ce74 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -28,8 +28,12 @@ arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c'
arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
arm_common_ss.add(when: 'CONFIG_MAX78000_SOC', if_true: files('max78000_soc.c'))
-arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
-arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
+arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files(
+ 'bcm2836.c',
+ 'bcm2838.c',
+ 'raspi.c',
+ 'raspi4b.c'
+))
arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 14/30] hw/core/machine: Allow dynamic registration of valid CPU types
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2025-10-20 22:13 ` [PATCH 13/30] hw/arm/raspi: " Philippe Mathieu-Daudé
@ 2025-10-20 22:13 ` Philippe Mathieu-Daudé
2025-10-20 22:13 ` [PATCH 15/30] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
` (15 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:13 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, qemu-arm, Anton Johansson,
Philippe Mathieu-Daudé, Eduardo Habkost, Marcel Apfelbaum,
Yanan Wang, Zhao Liu
Add MachineClass::get_valid_cpu_types(), a helper that
returns a dynamic list of CPU types. Since the helper
takes a MachineState argument, we know the machine is
created by the time we call it.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/boards.h | 4 ++++
hw/core/machine.c | 28 ++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a60e1d83390..8fc34579412 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -259,6 +259,9 @@ typedef struct {
* @smbios_memory_device_size:
* Default size of memory device,
* SMBIOS 3.1.0 "7.18 Memory Device (Type 17)"
+ * @get_valid_cpu_types:
+ * Returns a list of valid CPU types for this board. May be NULL
+ * if not needed.
*/
struct MachineClass {
/*< private >*/
@@ -305,6 +308,7 @@ struct MachineClass {
bool ignore_memory_transaction_failures;
int numa_mem_align_shift;
const char * const *valid_cpu_types;
+ GPtrArray *(*get_valid_cpu_types)(const MachineState *ms);
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 681adbb7ac5..5d9684fbc85 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1573,6 +1573,8 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
*/
if (mc->valid_cpu_types) {
assert(mc->valid_cpu_types[0] != NULL);
+ assert(!mc->get_valid_cpu_types);
+
for (i = 0; mc->valid_cpu_types[i]; i++) {
if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) {
break;
@@ -1599,6 +1601,32 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
error_append_hint(errp, "\n");
}
+ return false;
+ }
+ } else if (mc->get_valid_cpu_types) {
+ GPtrArray *vct = mc->get_valid_cpu_types(machine);
+ bool valid = false;
+
+ for (i = 0; i < vct->len; i++) {
+ if (object_class_dynamic_cast(oc, vct->pdata[i])) {
+ valid = true;
+ break;
+ }
+ }
+
+ if (!valid) {
+ g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
+
+ error_setg(errp, "Invalid CPU model: %s", requested);
+ error_append_hint(errp, "The valid models are: ");
+ for (i = 0; i < vct->len; i++) {
+ g_autofree char *model = cpu_model_from_type(vct->pdata[i]);
+ error_append_hint(errp, "%s%s",
+ model, i + 1 == vct->len ? "\n" : ", ");
+ }
+ }
+ g_ptr_array_free(vct, true);
+ if (!valid) {
return false;
}
}
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH 15/30] hw/arm/virt: Register valid CPU types dynamically
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2025-10-20 22:13 ` [PATCH 14/30] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
@ 2025-10-20 22:13 ` Philippe Mathieu-Daudé
2025-10-20 22:14 ` [PATCH v6 16/30] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
` (14 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:13 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, qemu-arm, Anton Johansson,
Philippe Mathieu-Daudé, Peter Maydell
Replace the static array returned as MachineClass::valid_cpu_types[]
by a runtime one generated by MachineClass::get_valid_cpu_types()
once the machine is created (its options being processed).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
FIXME: Richard comment:
>>> Why do these need to be strdup'ed?
>> g_slist_prepend() expects non-const.
>In a few patches this become a run-time check:
> if (target_aarch64()) {
> ...
> }
FIXME: Pierrick comment:
> It seems it would be more easy if get_valid_cpu_types simply return a const* char* const (same as existing valid_cpu_types), and caller does not have the responsibility to free it.
> This way, the list can be built either with a static array initializer, or with a dynamic GPtrArray, that we keep under a local static variable, so it has to be built only once. We can debate the leak introduced but I don't think it's really a problem.
---
hw/arm/virt.c | 59 ++++++++++++++++++++++++++++-----------------------
1 file changed, 32 insertions(+), 27 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 20e3f1094cb..e19da6fd901 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3256,36 +3256,41 @@ static int virt_hvf_get_physical_address_range(MachineState *ms)
return requested_ipa_size;
}
+static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
+{
+ GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
+
+#ifdef CONFIG_TCG
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
+#ifdef TARGET_AARCH64
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
+#endif /* TARGET_AARCH64 */
+#endif /* CONFIG_TCG */
+#ifdef TARGET_AARCH64
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
+#endif /* CONFIG_KVM || CONFIG_HVF */
+#endif /* TARGET_AARCH64 */
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
+
+ return vct;
+}
+
static void virt_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
- static const char * const valid_cpu_types[] = {
-#ifdef CONFIG_TCG
- ARM_CPU_TYPE_NAME("cortex-a7"),
- ARM_CPU_TYPE_NAME("cortex-a15"),
-#ifdef TARGET_AARCH64
- ARM_CPU_TYPE_NAME("cortex-a35"),
- ARM_CPU_TYPE_NAME("cortex-a55"),
- ARM_CPU_TYPE_NAME("cortex-a72"),
- ARM_CPU_TYPE_NAME("cortex-a76"),
- ARM_CPU_TYPE_NAME("cortex-a710"),
- ARM_CPU_TYPE_NAME("a64fx"),
- ARM_CPU_TYPE_NAME("neoverse-n1"),
- ARM_CPU_TYPE_NAME("neoverse-v1"),
- ARM_CPU_TYPE_NAME("neoverse-n2"),
-#endif /* TARGET_AARCH64 */
-#endif /* CONFIG_TCG */
-#ifdef TARGET_AARCH64
- ARM_CPU_TYPE_NAME("cortex-a53"),
- ARM_CPU_TYPE_NAME("cortex-a57"),
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
- ARM_CPU_TYPE_NAME("host"),
-#endif /* CONFIG_KVM || CONFIG_HVF */
-#endif /* TARGET_AARCH64 */
- ARM_CPU_TYPE_NAME("max"),
- NULL
- };
mc->init = machvirt_init;
/* Start with max_cpus set to 512, which is the maximum supported by KVM.
@@ -3311,7 +3316,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
#else
mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
#endif
- mc->valid_cpu_types = valid_cpu_types;
+ mc->get_valid_cpu_types = virt_get_valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 16/30] hw/arm/virt: Check accelerator availability at runtime
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2025-10-20 22:13 ` [PATCH 15/30] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
@ 2025-10-20 22:14 ` Philippe Mathieu-Daudé
2025-10-20 22:14 ` [PATCH v6 17/30] qemu/target_info: Add target_arm() helper Philippe Mathieu-Daudé
` (13 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé, Richard Henderson, Peter Maydell
It is not possible to call accelerator runtime helpers
when QOM types are registered, because they depend on
the parsing of the '-accel FOO' command line option,
which happens after main().
Now than get_valid_cpu_types() is called after
accelerator initializations, it is safe to call the
accelerator helpers:
main
+ configure_accelerators
+ qmp_x_exit_preconfig
+ qemu_init_board
+ machine_run_board_init
+ is_cpu_type_supported
Replace compile-time check on CONFIG_{ACCEL} by
runtime check on {accel}_enabled() helpers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/arm/virt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e19da6fd901..d3809754460 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3260,7 +3260,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
{
GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
-#ifdef CONFIG_TCG
+ if (tcg_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
#ifdef TARGET_AARCH64
@@ -3274,13 +3274,13 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
#endif /* TARGET_AARCH64 */
-#endif /* CONFIG_TCG */
+ }
#ifdef TARGET_AARCH64
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+ if (kvm_enabled() || hvf_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
-#endif /* CONFIG_KVM || CONFIG_HVF */
+ }
#endif /* TARGET_AARCH64 */
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 17/30] qemu/target_info: Add target_arm() helper
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2025-10-20 22:14 ` [PATCH v6 16/30] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
@ 2025-10-20 22:14 ` Philippe Mathieu-Daudé
2025-10-20 23:08 ` Pierrick Bouvier
2025-10-20 22:14 ` [PATCH v6 18/30] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
` (12 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé
Add a helper to distinct whether the binary is targetting
ARM (32-bit only) or not.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/qemu/target-info.h | 7 +++++++
target-info.c | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index abcf25db6fa..984fba3f42d 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -50,4 +50,11 @@ const char *target_cpu_type(void);
*/
bool target_big_endian(void);
+/**
+ * target_arm:
+ *
+ * Returns whether the target architecture is ARM (32-bit, not Aarch64).
+ */
+bool target_arm(void);
+
#endif
diff --git a/target-info.c b/target-info.c
index 3110ab32f75..40716bf4051 100644
--- a/target-info.c
+++ b/target-info.c
@@ -52,3 +52,8 @@ bool target_big_endian(void)
{
return target_endian_mode() == ENDIAN_MODE_BIG;
}
+
+bool target_arm(void)
+{
+ return target_arch() == SYS_EMU_TARGET_ARM;
+}
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 18/30] qemu/target_info: Add target_aarch64() helper
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2025-10-20 22:14 ` [PATCH v6 17/30] qemu/target_info: Add target_arm() helper Philippe Mathieu-Daudé
@ 2025-10-20 22:14 ` Philippe Mathieu-Daudé
2025-10-20 23:08 ` Pierrick Bouvier
2025-10-20 22:14 ` [PATCH v6 19/30] qemu/target-info: Add target_base_arch() Philippe Mathieu-Daudé
` (11 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé, Richard Henderson
Add a helper to distinct whether the binary is targetting
Aarch64 or not.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/qemu/target-info.h | 7 +++++++
target-info.c | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 984fba3f42d..e8fbdf19d53 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -57,4 +57,11 @@ bool target_big_endian(void);
*/
bool target_arm(void);
+/**
+ * target_aarch64:
+ *
+ * Returns whether the target architecture is Aarch64.
+ */
+bool target_aarch64(void);
+
#endif
diff --git a/target-info.c b/target-info.c
index 40716bf4051..e567cb4c40a 100644
--- a/target-info.c
+++ b/target-info.c
@@ -57,3 +57,8 @@ bool target_arm(void)
{
return target_arch() == SYS_EMU_TARGET_ARM;
}
+
+bool target_aarch64(void)
+{
+ return target_arch() == SYS_EMU_TARGET_AARCH64;
+}
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 18/30] qemu/target_info: Add target_aarch64() helper
2025-10-20 22:14 ` [PATCH v6 18/30] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
@ 2025-10-20 23:08 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Richard Henderson
On 2025-10-20 15:14, Philippe Mathieu-Daudé wrote:
> Add a helper to distinct whether the binary is targetting
> Aarch64 or not.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
> include/qemu/target-info.h | 7 +++++++
> target-info.c | 5 +++++
> 2 files changed, 12 insertions(+)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 19/30] qemu/target-info: Add target_base_arch()
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2025-10-20 22:14 ` [PATCH v6 18/30] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
@ 2025-10-20 22:14 ` Philippe Mathieu-Daudé
2025-10-20 23:15 ` Pierrick Bouvier
2025-10-20 22:14 ` [PATCH v6 20/30] qemu/target_info: Add target_base_arm() helper Philippe Mathieu-Daudé
` (10 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé
When multiple QEMU targets are variants (word size, endianness)
of the same base architecture, target_base_arch() returns this
base. For example, for the Aarch64 target it will return
SYS_EMU_TARGET_ARM as common base.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/qemu/target-info-impl.h | 2 ++
include/qemu/target-info-qapi.h | 7 +++++++
target-info-stub.c | 1 +
target-info.c | 10 ++++++++++
4 files changed, 20 insertions(+)
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index e446585bf53..2c171f8359b 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -17,6 +17,8 @@ typedef struct TargetInfo {
const char *target_name;
/* related to TARGET_ARCH definition */
SysEmuTarget target_arch;
+ /* related to TARGET_BASE_ARCH definition (target/${base_arch}/ path) */
+ SysEmuTarget target_base_arch;
/* runtime equivalent of TARGET_LONG_BITS definition */
unsigned long_bits;
/* runtime equivalent of CPU_RESOLVING_TYPE definition */
diff --git a/include/qemu/target-info-qapi.h b/include/qemu/target-info-qapi.h
index d5ce0523238..65ed4ca8eea 100644
--- a/include/qemu/target-info-qapi.h
+++ b/include/qemu/target-info-qapi.h
@@ -19,6 +19,13 @@
*/
SysEmuTarget target_arch(void);
+/**
+ * target_base_arch:
+ *
+ * Returns: QAPI SysEmuTarget enum (i.e. SYS_EMU_TARGET_I386).
+ */
+SysEmuTarget target_base_arch(void);
+
/**
* target_endian_mode:
*
diff --git a/target-info-stub.c b/target-info-stub.c
index d96d8249c1d..d2cfca1b4c2 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -19,6 +19,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
static const TargetInfo target_info_stub = {
.target_name = TARGET_NAME,
.target_arch = SYS_EMU_TARGET__MAX,
+ .target_base_arch = SYS_EMU_TARGET__MAX,
.long_bits = TARGET_LONG_BITS,
.cpu_type = CPU_RESOLVING_TYPE,
.machine_typename = TYPE_MACHINE,
diff --git a/target-info.c b/target-info.c
index e567cb4c40a..332198e40a2 100644
--- a/target-info.c
+++ b/target-info.c
@@ -33,6 +33,16 @@ SysEmuTarget target_arch(void)
return arch;
}
+SysEmuTarget target_base_arch(void)
+{
+ SysEmuTarget base_arch = target_info()->target_base_arch;
+
+ if (base_arch == SYS_EMU_TARGET__MAX) {
+ base_arch = target_arch();
+ }
+ return base_arch;
+}
+
const char *target_cpu_type(void)
{
return target_info()->cpu_type;
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 19/30] qemu/target-info: Add target_base_arch()
2025-10-20 22:14 ` [PATCH v6 19/30] qemu/target-info: Add target_base_arch() Philippe Mathieu-Daudé
@ 2025-10-20 23:15 ` Pierrick Bouvier
2025-10-21 7:53 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Anton Johansson, qemu-arm
On 2025-10-20 15:14, Philippe Mathieu-Daudé wrote:
> When multiple QEMU targets are variants (word size, endianness)
> of the same base architecture, target_base_arch() returns this
> base. For example, for the Aarch64 target it will return
> SYS_EMU_TARGET_ARM as common base.
>
I'm not sure that reusing semantic on a subset of this enum is the best
idea, so many things can go wrong.
More widely, I don't know where we would need to access this, versus
specific functions like target_base_arm().
If a code needs to check various base archs target_base_*, or it can use
a switch with all variants.
If we really want to have this target_base concept, at least it deserves
it's own enum, separate from SYS_EMU_TARGET.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/qemu/target-info-impl.h | 2 ++
> include/qemu/target-info-qapi.h | 7 +++++++
> target-info-stub.c | 1 +
> target-info.c | 10 ++++++++++
> 4 files changed, 20 insertions(+)
>
> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
> index e446585bf53..2c171f8359b 100644
> --- a/include/qemu/target-info-impl.h
> +++ b/include/qemu/target-info-impl.h
> @@ -17,6 +17,8 @@ typedef struct TargetInfo {
> const char *target_name;
> /* related to TARGET_ARCH definition */
> SysEmuTarget target_arch;
> + /* related to TARGET_BASE_ARCH definition (target/${base_arch}/ path) */
> + SysEmuTarget target_base_arch;
> /* runtime equivalent of TARGET_LONG_BITS definition */
> unsigned long_bits;
> /* runtime equivalent of CPU_RESOLVING_TYPE definition */
> diff --git a/include/qemu/target-info-qapi.h b/include/qemu/target-info-qapi.h
> index d5ce0523238..65ed4ca8eea 100644
> --- a/include/qemu/target-info-qapi.h
> +++ b/include/qemu/target-info-qapi.h
> @@ -19,6 +19,13 @@
> */
> SysEmuTarget target_arch(void);
>
> +/**
> + * target_base_arch:
> + *
> + * Returns: QAPI SysEmuTarget enum (i.e. SYS_EMU_TARGET_I386).
> + */
> +SysEmuTarget target_base_arch(void);
> +
> /**
> * target_endian_mode:
> *
> diff --git a/target-info-stub.c b/target-info-stub.c
> index d96d8249c1d..d2cfca1b4c2 100644
> --- a/target-info-stub.c
> +++ b/target-info-stub.c
> @@ -19,6 +19,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
> static const TargetInfo target_info_stub = {
> .target_name = TARGET_NAME,
> .target_arch = SYS_EMU_TARGET__MAX,
> + .target_base_arch = SYS_EMU_TARGET__MAX,
And nothing can enforce base and arch match by design, which is a
problem IMHO.
> .long_bits = TARGET_LONG_BITS,
> .cpu_type = CPU_RESOLVING_TYPE,
> .machine_typename = TYPE_MACHINE,
> diff --git a/target-info.c b/target-info.c
> index e567cb4c40a..332198e40a2 100644
> --- a/target-info.c
> +++ b/target-info.c
> @@ -33,6 +33,16 @@ SysEmuTarget target_arch(void)
> return arch;
> }
>
> +SysEmuTarget target_base_arch(void)
> +{
> + SysEmuTarget base_arch = target_info()->target_base_arch;
> +
> + if (base_arch == SYS_EMU_TARGET__MAX) {
> + base_arch = target_arch();
> + }
> + return base_arch;
More confusing, we can eventually return a non base arch if base arch
was not correctly set above.
> +}
> +
> const char *target_cpu_type(void)
> {
> return target_info()->cpu_type;
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PATCH v6 19/30] qemu/target-info: Add target_base_arch()
2025-10-20 23:15 ` Pierrick Bouvier
@ 2025-10-21 7:53 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-21 7:53 UTC (permalink / raw)
To: Pierrick Bouvier, qemu-devel; +Cc: Anton Johansson, qemu-arm
On 21/10/25 01:15, Pierrick Bouvier wrote:
> On 2025-10-20 15:14, Philippe Mathieu-Daudé wrote:
>> When multiple QEMU targets are variants (word size, endianness)
>> of the same base architecture, target_base_arch() returns this
>> base. For example, for the Aarch64 target it will return
>> SYS_EMU_TARGET_ARM as common base.
>>
>
> I'm not sure that reusing semantic on a subset of this enum is the best
> idea, so many things can go wrong.
>
> More widely, I don't know where we would need to access this, versus
> specific functions like target_base_arm().
> If a code needs to check various base archs target_base_*, or it can use
> a switch with all variants.
Yeah, good point. I'll just drop this single patch.
>
> If we really want to have this target_base concept, at least it deserves
> it's own enum, separate from SYS_EMU_TARGET.
>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> include/qemu/target-info-impl.h | 2 ++
>> include/qemu/target-info-qapi.h | 7 +++++++
>> target-info-stub.c | 1 +
>> target-info.c | 10 ++++++++++
>> 4 files changed, 20 insertions(+)
>>
>> diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-
>> info-impl.h
>> index e446585bf53..2c171f8359b 100644
>> --- a/include/qemu/target-info-impl.h
>> +++ b/include/qemu/target-info-impl.h
>> @@ -17,6 +17,8 @@ typedef struct TargetInfo {
>> const char *target_name;
>> /* related to TARGET_ARCH definition */
>> SysEmuTarget target_arch;
>> + /* related to TARGET_BASE_ARCH definition (target/${base_arch}/
>> path) */
>> + SysEmuTarget target_base_arch;
>> /* runtime equivalent of TARGET_LONG_BITS definition */
>> unsigned long_bits;
>> /* runtime equivalent of CPU_RESOLVING_TYPE definition */
>> diff --git a/include/qemu/target-info-qapi.h b/include/qemu/target-
>> info-qapi.h
>> index d5ce0523238..65ed4ca8eea 100644
>> --- a/include/qemu/target-info-qapi.h
>> +++ b/include/qemu/target-info-qapi.h
>> @@ -19,6 +19,13 @@
>> */
>> SysEmuTarget target_arch(void);
>> +/**
>> + * target_base_arch:
>> + *
>> + * Returns: QAPI SysEmuTarget enum (i.e. SYS_EMU_TARGET_I386).
>> + */
>> +SysEmuTarget target_base_arch(void);
>> +
>> /**
>> * target_endian_mode:
>> *
>> diff --git a/target-info-stub.c b/target-info-stub.c
>> index d96d8249c1d..d2cfca1b4c2 100644
>> --- a/target-info-stub.c
>> +++ b/target-info-stub.c
>> @@ -19,6 +19,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=
>> sizeof(CPUState));
>> static const TargetInfo target_info_stub = {
>> .target_name = TARGET_NAME,
>> .target_arch = SYS_EMU_TARGET__MAX,
>> + .target_base_arch = SYS_EMU_TARGET__MAX,
>
> And nothing can enforce base and arch match by design, which is a
> problem IMHO.
>
>> .long_bits = TARGET_LONG_BITS,
>> .cpu_type = CPU_RESOLVING_TYPE,
>> .machine_typename = TYPE_MACHINE,
>> diff --git a/target-info.c b/target-info.c
>> index e567cb4c40a..332198e40a2 100644
>> --- a/target-info.c
>> +++ b/target-info.c
>> @@ -33,6 +33,16 @@ SysEmuTarget target_arch(void)
>> return arch;
>> }
>> +SysEmuTarget target_base_arch(void)
>> +{
>> + SysEmuTarget base_arch = target_info()->target_base_arch;
>> +
>> + if (base_arch == SYS_EMU_TARGET__MAX) {
>> + base_arch = target_arch();
>> + }
>> + return base_arch;
>
> More confusing, we can eventually return a non base arch if base arch
> was not correctly set above.
>
>> +}
>> +
>> const char *target_cpu_type(void)
>> {
>> return target_info()->cpu_type;
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 20/30] qemu/target_info: Add target_base_arm() helper
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2025-10-20 22:14 ` [PATCH v6 19/30] qemu/target-info: Add target_base_arch() Philippe Mathieu-Daudé
@ 2025-10-20 22:14 ` Philippe Mathieu-Daudé
2025-10-20 23:16 ` Pierrick Bouvier
2025-10-20 22:14 ` [PATCH v6 21/30] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
` (9 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé
Add a helper to check whether the target base architecture
is ARM (either 32-bit or 64-bit).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/qemu/target-info.h | 7 +++++++
target-info.c | 11 +++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index e8fbdf19d53..62359622232 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -50,6 +50,13 @@ const char *target_cpu_type(void);
*/
bool target_big_endian(void);
+/**
+ * target_base_arm:
+ *
+ * Returns whether the target architecture is ARM or Aarch64.
+ */
+bool target_base_arm(void);
+
/**
* target_arm:
*
diff --git a/target-info.c b/target-info.c
index 332198e40a2..f661b1af289 100644
--- a/target-info.c
+++ b/target-info.c
@@ -63,6 +63,17 @@ bool target_big_endian(void)
return target_endian_mode() == ENDIAN_MODE_BIG;
}
+bool target_base_arm(void)
+{
+ switch (target_arch()) {
+ case SYS_EMU_TARGET_ARM:
+ case SYS_EMU_TARGET_AARCH64:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool target_arm(void)
{
return target_arch() == SYS_EMU_TARGET_ARM;
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 20/30] qemu/target_info: Add target_base_arm() helper
2025-10-20 22:14 ` [PATCH v6 20/30] qemu/target_info: Add target_base_arm() helper Philippe Mathieu-Daudé
@ 2025-10-20 23:16 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Anton Johansson, qemu-arm
On 2025-10-20 15:14, Philippe Mathieu-Daudé wrote:
> Add a helper to check whether the target base architecture
> is ARM (either 32-bit or 64-bit).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/qemu/target-info.h | 7 +++++++
> target-info.c | 11 +++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
> index e8fbdf19d53..62359622232 100644
> --- a/include/qemu/target-info.h
> +++ b/include/qemu/target-info.h
> @@ -50,6 +50,13 @@ const char *target_cpu_type(void);
> */
> bool target_big_endian(void);
>
> +/**
> + * target_base_arm:
> + *
> + * Returns whether the target architecture is ARM or Aarch64.
> + */
> +bool target_base_arm(void);
> +
> /**
> * target_arm:
> *
> diff --git a/target-info.c b/target-info.c
> index 332198e40a2..f661b1af289 100644
> --- a/target-info.c
> +++ b/target-info.c
> @@ -63,6 +63,17 @@ bool target_big_endian(void)
> return target_endian_mode() == ENDIAN_MODE_BIG;
> }
>
> +bool target_base_arm(void)
> +{
> + switch (target_arch()) {
> + case SYS_EMU_TARGET_ARM:
> + case SYS_EMU_TARGET_AARCH64:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> bool target_arm(void)
> {
> return target_arch() == SYS_EMU_TARGET_ARM;
That's good, and we can extend that to all other base arch accordingly.
It's a small amount of boilerplate for something that is safe by design
and can't be misused.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 21/30] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2025-10-20 22:14 ` [PATCH v6 20/30] qemu/target_info: Add target_base_arm() helper Philippe Mathieu-Daudé
@ 2025-10-20 22:14 ` Philippe Mathieu-Daudé
2025-10-20 23:16 ` Pierrick Bouvier
2025-10-20 22:15 ` [PATCH v6 22/30] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
` (8 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé, Richard Henderson, Peter Maydell
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_aarch64() helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/arm/virt.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d3809754460..dda8edb2745 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -32,6 +32,7 @@
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/option.h"
+#include "qemu/target-info.h"
#include "monitor/qdev.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
@@ -3263,7 +3264,8 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
if (tcg_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
-#ifdef TARGET_AARCH64
+ }
+ if (tcg_enabled() && target_aarch64()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
@@ -3273,15 +3275,14 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
-#endif /* TARGET_AARCH64 */
}
-#ifdef TARGET_AARCH64
+ if (target_aarch64()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
if (kvm_enabled() || hvf_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
}
-#endif /* TARGET_AARCH64 */
+ }
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
return vct;
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 21/30] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
2025-10-20 22:14 ` [PATCH v6 21/30] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
@ 2025-10-20 23:16 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Richard Henderson, Peter Maydell
On 2025-10-20 15:14, Philippe Mathieu-Daudé wrote:
> Replace the target-specific TARGET_AARCH64 definition
> by a call to the generic target_aarch64() helper.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
> hw/arm/virt.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index d3809754460..dda8edb2745 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -32,6 +32,7 @@
> #include "qemu/datadir.h"
> #include "qemu/units.h"
> #include "qemu/option.h"
> +#include "qemu/target-info.h"
> #include "monitor/qdev.h"
> #include "hw/sysbus.h"
> #include "hw/arm/boot.h"
> @@ -3263,7 +3264,8 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
> if (tcg_enabled()) {
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
> -#ifdef TARGET_AARCH64
> + }
> + if (tcg_enabled() && target_aarch64()) {
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
> @@ -3273,15 +3275,14 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
> -#endif /* TARGET_AARCH64 */
> }
> -#ifdef TARGET_AARCH64
> + if (target_aarch64()) {
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
> if (kvm_enabled() || hvf_enabled()) {
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
> }
> -#endif /* TARGET_AARCH64 */
> + }
> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
>
> return vct;
❤️
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 22/30] hw/core: Introduce MachineClass::get_default_cpu_type() helper
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2025-10-20 22:14 ` [PATCH v6 21/30] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
@ 2025-10-20 22:15 ` Philippe Mathieu-Daudé
2025-10-20 22:15 ` [PATCH v6 23/30] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
` (7 subsequent siblings)
29 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:15 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Yanan Wang, Zhao Liu, Paolo Bonzini
MachineClass::get_default_cpu_type() runs once the machine is
created, being able to evaluate runtime checks; it returns the
machine default CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/hw/boards.h | 6 ++++++
hw/core/machine.c | 10 ++++++++++
system/vl.c | 2 +-
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 8fc34579412..5f0fa5f56c3 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -25,6 +25,11 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
extern MachineState *current_machine;
+/**
+ * machine_default_cpu_type: Return the machine default CPU type.
+ * @ms: Machine state
+ */
+const char *machine_default_cpu_type(const MachineState *ms);
/**
* machine_class_default_cpu_type: Return the machine default CPU type.
* @mc: Machine class
@@ -309,6 +314,7 @@ struct MachineClass {
int numa_mem_align_shift;
const char * const *valid_cpu_types;
GPtrArray *(*get_valid_cpu_types)(const MachineState *ms);
+ const char *(*get_default_cpu_type)(const MachineState *ms);
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 5d9684fbc85..bf0530b25cc 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1559,6 +1559,16 @@ const char *machine_class_default_cpu_type(MachineClass *mc)
return mc->default_cpu_type;
}
+const char *machine_default_cpu_type(const MachineState *ms)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ if (mc->get_default_cpu_type) {
+ return mc->get_default_cpu_type(ms);
+ }
+ return machine_class_default_cpu_type(mc);
+}
+
static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
diff --git a/system/vl.c b/system/vl.c
index a96063f9901..fd98ea52d9c 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -3817,7 +3817,7 @@ void qemu_init(int argc, char **argv)
migration_object_init();
/* parse features once if machine provides default cpu_type */
- current_machine->cpu_type = machine_class_default_cpu_type(machine_class);
+ current_machine->cpu_type = machine_default_cpu_type(current_machine);
if (cpu_option) {
current_machine->cpu_type = parse_cpu_option(cpu_option);
}
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 23/30] hw/arm/virt: Get default CPU type at runtime
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2025-10-20 22:15 ` [PATCH v6 22/30] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
@ 2025-10-20 22:15 ` Philippe Mathieu-Daudé
2025-10-20 23:37 ` Pierrick Bouvier
2025-10-20 22:15 ` [PATCH v6 24/30] hw/arm/sbsa-ref: Include missing 'cpu.h' header Philippe Mathieu-Daudé
` (6 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:15 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé, Richard Henderson, Zhang Chen,
Peter Maydell
Prefer MachineClass::get_default_cpu_type() over
MachineClass::default_cpu_type to get CPU type,
evaluating TCG availability at runtime calling
tcg_enabled().
It's worth noting that this is a behavior change:
- Previously only
./configure --disable-tcg --enable-kvm
./qemu-system-aarch64 -M virt -accel kvm
would default to 'max' and
./configure --enable-tcg --enable-kvm
./qemu-system-aarch64 -M virt -accel kvm
would default to 'cortex-a15'.
- Afterward, -accel kvm will always default to 'max'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhang Chen <zhangckid@gmail.com>
---
hw/arm/virt.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index dda8edb2745..d07cfe16512 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3257,6 +3257,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms)
return requested_ipa_size;
}
+static const char *virt_get_default_cpu_type(const MachineState *ms)
+{
+ return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15")
+ : ARM_CPU_TYPE_NAME("max");
+}
+
static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
{
GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
@@ -3312,11 +3318,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
mc->minimum_page_bits = 12;
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
-#ifdef CONFIG_TCG
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-#else
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
-#endif
+ mc->get_default_cpu_type = virt_get_default_cpu_type;
mc->get_valid_cpu_types = virt_get_valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 23/30] hw/arm/virt: Get default CPU type at runtime
2025-10-20 22:15 ` [PATCH v6 23/30] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
@ 2025-10-20 23:37 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Richard Henderson, Zhang Chen,
Peter Maydell
On 2025-10-20 15:15, Philippe Mathieu-Daudé wrote:
> Prefer MachineClass::get_default_cpu_type() over
> MachineClass::default_cpu_type to get CPU type,
> evaluating TCG availability at runtime calling
> tcg_enabled().
>
> It's worth noting that this is a behavior change:
>
> - Previously only
>
> ./configure --disable-tcg --enable-kvm
> ./qemu-system-aarch64 -M virt -accel kvm
>
> would default to 'max' and
>
> ./configure --enable-tcg --enable-kvm
> ./qemu-system-aarch64 -M virt -accel kvm
>
> would default to 'cortex-a15'.
>
> - Afterward, -accel kvm will always default to 'max'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Zhang Chen <zhangckid@gmail.com>
> ---
> hw/arm/virt.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 24/30] hw/arm/sbsa-ref: Include missing 'cpu.h' header
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2025-10-20 22:15 ` [PATCH v6 23/30] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
@ 2025-10-20 22:15 ` Philippe Mathieu-Daudé
2025-10-20 23:38 ` Pierrick Bouvier
2025-10-20 22:20 ` [PATCH v6 25/30] hw/arm/sbsa-ref: Build only once Philippe Mathieu-Daudé
` (5 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:15 UTC (permalink / raw)
To: qemu-devel
Cc: Pierrick Bouvier, Anton Johansson, qemu-arm,
Philippe Mathieu-Daudé, Radoslaw Biernacki, Peter Maydell,
Leif Lindholm
"cpu.h" is indirectly pulled in by another header. Include
it explicitly in order to avoid when changing default CPPFLAGS path:
hw/arm/sbsa-ref.c:162:25: error: use of undeclared identifier 'ARM_DEFAULT_CPUS_PER_CLUSTER'
162 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
| ^
hw/arm/sbsa-ref.c:163:12: error: call to undeclared function 'arm_build_mp_affinity'
163 | return arm_build_mp_affinity(idx, clustersz);
| ^
hw/arm/sbsa-ref.c:746:25: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED'
746 | sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index cf6e6eb208a..2205500a8da 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -52,6 +52,7 @@
#include "net/net.h"
#include "qobject/qlist.h"
#include "qom/object.h"
+#include "target/arm/cpu.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 24/30] hw/arm/sbsa-ref: Include missing 'cpu.h' header
2025-10-20 22:15 ` [PATCH v6 24/30] hw/arm/sbsa-ref: Include missing 'cpu.h' header Philippe Mathieu-Daudé
@ 2025-10-20 23:38 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Anton Johansson, qemu-arm, Radoslaw Biernacki, Peter Maydell,
Leif Lindholm
On 2025-10-20 15:15, Philippe Mathieu-Daudé wrote:
> "cpu.h" is indirectly pulled in by another header. Include
> it explicitly in order to avoid when changing default CPPFLAGS path:
>
> hw/arm/sbsa-ref.c:162:25: error: use of undeclared identifier 'ARM_DEFAULT_CPUS_PER_CLUSTER'
> 162 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
> | ^
> hw/arm/sbsa-ref.c:163:12: error: call to undeclared function 'arm_build_mp_affinity'
> 163 | return arm_build_mp_affinity(idx, clustersz);
> | ^
> hw/arm/sbsa-ref.c:746:25: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED'
> 746 | sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
> | ^
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/sbsa-ref.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 25/30] hw/arm/sbsa-ref: Build only once
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (23 preceding siblings ...)
2025-10-20 22:15 ` [PATCH v6 24/30] hw/arm/sbsa-ref: Include missing 'cpu.h' header Philippe Mathieu-Daudé
@ 2025-10-20 22:20 ` Philippe Mathieu-Daudé
2025-10-20 23:39 ` Pierrick Bouvier
2025-10-20 22:20 ` [PATCH v6 26/30] hw/arm/virt-acpi-build: Include missing 'cpu.h' header Philippe Mathieu-Daudé
` (4 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Pierrick Bouvier,
Philippe Mathieu-Daudé, Peter Maydell
Since previous commit allowed the use of accelerator definitions
in common code, we can now move sbsa-ref.c to arm_common_ss[].
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index a12d690ce74..fbd5e8da79c 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -14,7 +14,7 @@ arm_common_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32
arm_common_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
arm_common_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_boards.c'))
arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
-arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
+arm_common_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 25/30] hw/arm/sbsa-ref: Build only once
2025-10-20 22:20 ` [PATCH v6 25/30] hw/arm/sbsa-ref: Build only once Philippe Mathieu-Daudé
@ 2025-10-20 23:39 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Peter Maydell
On 2025-10-20 15:20, Philippe Mathieu-Daudé wrote:
> Since previous commit allowed the use of accelerator definitions
> in common code, we can now move sbsa-ref.c to arm_common_ss[].
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 26/30] hw/arm/virt-acpi-build: Include missing 'cpu.h' header
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (24 preceding siblings ...)
2025-10-20 22:20 ` [PATCH v6 25/30] hw/arm/sbsa-ref: Build only once Philippe Mathieu-Daudé
@ 2025-10-20 22:20 ` Philippe Mathieu-Daudé
2025-10-20 23:40 ` Pierrick Bouvier
2025-10-20 22:20 ` [PATCH v6 27/30] hw/arm/virt-acpi-build: Build only once Philippe Mathieu-Daudé
` (3 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Pierrick Bouvier,
Philippe Mathieu-Daudé, Peter Maydell, Shannon Zhao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha
"cpu.h" is indirectly pulled in by another header. Include
it explicitly in order to avoid when changing default CPPFLAGS path:
hw/arm/virt-acpi-build.c:903:34: error: call to undeclared function 'arm_feature';
903 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
| ^
hw/arm/virt-acpi-build.c:903:53: error: incomplete definition of type 'ARMCPU' (aka 'struct ArchCPU')
903 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
| ~~~~~~^
include/qemu/typedefs.h:30:16: note: forward declaration of 'struct ArchCPU'
30 | typedef struct ArchCPU ArchCPU;
| ^
hw/arm/virt-acpi-build.c:903:60: error: use of undeclared identifier 'ARM_FEATURE_PMU'
903 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
| ^
hw/arm/virt-acpi-build.c:993:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED'
993 | case QEMU_PSCI_CONDUIT_DISABLED:
| ^
hw/arm/virt-acpi-build.c:996:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_HVC'
996 | case QEMU_PSCI_CONDUIT_HVC:
| ^
hw/arm/virt-acpi-build.c:1000:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_SMC'
1000 | case QEMU_PSCI_CONDUIT_SMC:
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/virt-acpi-build.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 8bb6b605154..200e2a1da70 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -62,6 +62,7 @@
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
#include "hw/virtio/virtio-acpi.h"
+#include "target/arm/cpu.h"
#include "target/arm/multiprocessing.h"
#define ARM_SPI_BASE 32
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 26/30] hw/arm/virt-acpi-build: Include missing 'cpu.h' header
2025-10-20 22:20 ` [PATCH v6 26/30] hw/arm/virt-acpi-build: Include missing 'cpu.h' header Philippe Mathieu-Daudé
@ 2025-10-20 23:40 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Peter Maydell,
Shannon Zhao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha
On 2025-10-20 15:20, Philippe Mathieu-Daudé wrote:
> "cpu.h" is indirectly pulled in by another header. Include
> it explicitly in order to avoid when changing default CPPFLAGS path:
>
> hw/arm/virt-acpi-build.c:903:34: error: call to undeclared function 'arm_feature';
> 903 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
> | ^
> hw/arm/virt-acpi-build.c:903:53: error: incomplete definition of type 'ARMCPU' (aka 'struct ArchCPU')
> 903 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
> | ~~~~~~^
> include/qemu/typedefs.h:30:16: note: forward declaration of 'struct ArchCPU'
> 30 | typedef struct ArchCPU ArchCPU;
> | ^
> hw/arm/virt-acpi-build.c:903:60: error: use of undeclared identifier 'ARM_FEATURE_PMU'
> 903 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
> | ^
> hw/arm/virt-acpi-build.c:993:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_DISABLED'
> 993 | case QEMU_PSCI_CONDUIT_DISABLED:
> | ^
> hw/arm/virt-acpi-build.c:996:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_HVC'
> 996 | case QEMU_PSCI_CONDUIT_HVC:
> | ^
> hw/arm/virt-acpi-build.c:1000:10: error: use of undeclared identifier 'QEMU_PSCI_CONDUIT_SMC'
> 1000 | case QEMU_PSCI_CONDUIT_SMC:
> | ^
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 27/30] hw/arm/virt-acpi-build: Build only once
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (25 preceding siblings ...)
2025-10-20 22:20 ` [PATCH v6 26/30] hw/arm/virt-acpi-build: Include missing 'cpu.h' header Philippe Mathieu-Daudé
@ 2025-10-20 22:20 ` Philippe Mathieu-Daudé
2025-10-20 23:40 ` Pierrick Bouvier
2025-10-20 22:20 ` [PATCH v6 28/30] hw/arm/virt: " Philippe Mathieu-Daudé
` (2 subsequent siblings)
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Pierrick Bouvier,
Philippe Mathieu-Daudé, Peter Maydell
Previous commits removed the target-specificities,
we can now move virt-acpi-build.c to arm_common_ss[].
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index fbd5e8da79c..4dfc7813191 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,7 +1,7 @@
arm_ss = ss.source_set()
arm_common_ss = ss.source_set()
arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
-arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
+arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
arm_common_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 27/30] hw/arm/virt-acpi-build: Build only once
2025-10-20 22:20 ` [PATCH v6 27/30] hw/arm/virt-acpi-build: Build only once Philippe Mathieu-Daudé
@ 2025-10-20 23:40 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Peter Maydell
On 2025-10-20 15:20, Philippe Mathieu-Daudé wrote:
> Previous commits removed the target-specificities,
> we can now move virt-acpi-build.c to arm_common_ss[].
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 28/30] hw/arm/virt: Build only once
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (26 preceding siblings ...)
2025-10-20 22:20 ` [PATCH v6 27/30] hw/arm/virt-acpi-build: Build only once Philippe Mathieu-Daudé
@ 2025-10-20 22:20 ` Philippe Mathieu-Daudé
2025-10-20 23:40 ` Pierrick Bouvier
2025-10-20 22:20 ` [PATCH v6 29/30] hw/arm/meson: Move Xen files to arm_common_ss[] Philippe Mathieu-Daudé
2025-10-20 22:20 ` [PATCH v6 30/30] hw/arm/meson: Remove now unused arm_ss[] source set Philippe Mathieu-Daudé
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Pierrick Bouvier,
Philippe Mathieu-Daudé, Peter Maydell
Previous commits removed the TARGET_AARCH64 uses in virt.c,
we can now move it to arm_common_ss[] and build it once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 4dfc7813191..f9d615e360b 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,6 +1,6 @@
arm_ss = ss.source_set()
arm_common_ss = ss.source_set()
-arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
+arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PATCH v6 28/30] hw/arm/virt: Build only once
2025-10-20 22:20 ` [PATCH v6 28/30] hw/arm/virt: " Philippe Mathieu-Daudé
@ 2025-10-20 23:40 ` Pierrick Bouvier
0 siblings, 0 replies; 51+ messages in thread
From: Pierrick Bouvier @ 2025-10-20 23:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Peter Maydell
On 2025-10-20 15:20, Philippe Mathieu-Daudé wrote:
> Previous commits removed the TARGET_AARCH64 uses in virt.c,
> we can now move it to arm_common_ss[] and build it once.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v6 29/30] hw/arm/meson: Move Xen files to arm_common_ss[]
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (27 preceding siblings ...)
2025-10-20 22:20 ` [PATCH v6 28/30] hw/arm/virt: " Philippe Mathieu-Daudé
@ 2025-10-20 22:20 ` Philippe Mathieu-Daudé
2025-10-20 23:41 ` Pierrick Bouvier
2025-10-20 22:20 ` [PATCH v6 30/30] hw/arm/meson: Remove now unused arm_ss[] source set Philippe Mathieu-Daudé
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Pierrick Bouvier,
Philippe Mathieu-Daudé, Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index f9d615e360b..28106de94b0 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -68,7 +68,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c'))
arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
-arm_ss.add(when: 'CONFIG_XEN', if_true: files(
+arm_common_ss.add(when: 'CONFIG_XEN', if_true: files(
'xen-stubs.c',
'xen-pvh.c',
))
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PATCH v6 30/30] hw/arm/meson: Remove now unused arm_ss[] source set
2025-10-20 22:09 [PATCH v6 00/30] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (28 preceding siblings ...)
2025-10-20 22:20 ` [PATCH v6 29/30] hw/arm/meson: Move Xen files to arm_common_ss[] Philippe Mathieu-Daudé
@ 2025-10-20 22:20 ` Philippe Mathieu-Daudé
2025-10-20 23:41 ` Pierrick Bouvier
29 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: Zhao Liu, Luc Michel, Anton Johansson, qemu-arm, Pierrick Bouvier,
Philippe Mathieu-Daudé, Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/meson.build | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 28106de94b0..de562c22625 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,4 +1,3 @@
-arm_ss = ss.source_set()
arm_common_ss = ss.source_set()
arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
@@ -87,5 +86,4 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
arm_common_ss.add(files('boot.c'))
-hw_arch += {'arm': arm_ss}
hw_common_arch += {'arm': arm_common_ss}
--
2.51.0
^ permalink raw reply related [flat|nested] 51+ messages in thread