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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5b3c56sm17459246f8f.18.2025.10.20.15.15.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 20 Oct 2025 15:15:14 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Anton Johansson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 17/30] qemu/target_info: Add target_arm() helper Date: Tue, 21 Oct 2025 00:14:55 +0200 Message-ID: <20251020221508.67413-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020220941.65269-1-philmd@linaro.org> References: <20251020220941.65269-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add a helper to distinct whether the binary is targetting ARM (32-bit only) or not. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index abcf25db6fa..984fba3f42d 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -50,4 +50,11 @@ const char *target_cpu_type(void); */ bool target_big_endian(void); +/** + * target_arm: + * + * Returns whether the target architecture is ARM (32-bit, not Aarch64). + */ +bool target_arm(void); + #endif diff --git a/target-info.c b/target-info.c index 3110ab32f75..40716bf4051 100644 --- a/target-info.c +++ b/target-info.c @@ -52,3 +52,8 @@ bool target_big_endian(void) { return target_endian_mode() == ENDIAN_MODE_BIG; } + +bool target_arm(void) +{ + return target_arch() == SYS_EMU_TARGET_ARM; +} -- 2.51.0