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Iglesias" , Aurelien Jarno , Richard Henderson , Thomas Huth , Max Filippov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Michael Rolnik , Song Gao , qemu-riscv@nongnu.org, Aleksandar Rikalo , Julian Ganz Subject: [PATCH 16/35] target/loongarch: call plugin trap callbacks Date: Mon, 27 Oct 2025 11:03:23 +0000 Message-ID: <20251027110344.2289945-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251027110344.2289945-1-alex.bennee@linaro.org> References: <20251027110344.2289945-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org From: Julian Ganz We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for loongarch targets. This architecture has one special "exception" for interrupts and no host calls. Reviewed-by: Richard Henderson Signed-off-by: Julian Ganz Reviewed-by: Song Gao Signed-off-by: Alex Bennée --- target/loongarch/tcg/tcg_cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 82b54e6dc3c..9d077c56d9d 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -8,6 +8,7 @@ #include "qemu/accel.h" #include "qemu/error-report.h" #include "qemu/log.h" +#include "qemu/plugin.h" #include "accel/accel-cpu-target.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" @@ -80,6 +81,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) int cause = -1; bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); + uint64_t last_pc = env->pc; if (cs->exception_index != EXCCODE_INT) { qemu_log_mask(CPU_LOG_INT, @@ -190,6 +192,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) __func__, env->pc, env->CSR_ERA, cause, env->CSR_BADV, env->CSR_DERA, vector, env->CSR_ECFG, env->CSR_ESTAT); + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); } else { if (tlbfill) { set_pc(env, env->CSR_TLBRENTRY); @@ -208,6 +211,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, env->CSR_BADI, env->gpr[11], cs->cpu_index, env->CSR_ASID); + qemu_plugin_vcpu_exception_cb(cs, last_pc); } cs->exception_index = -1; } -- 2.47.3