[PATCH v7 16/22] hw/i3c/dw-i3c: Add controller resets

Jamin Lin
2026-02-25T02:18:03Z

Adds behavior to the device reset register.

Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/i3c/dw-i3c.c | 117 ++++++++++++++++++++++++++++++++++++++++++++
hw/i3c/trace-events | 1 +
2 files changed, 118 insertions(+)

diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index b6ec0d9579..d742458129 100644
--- a/hw/i3c/dw-i3c.c
+++ b/hw/i3c/dw-i3c.c
@@ -860,6 +860,122 @@ static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val)
dw_i3c_update_irq(s);
}

+static void dw_i3c_cmd_queue_reset(DWI3C *s)
+{
+ fifo32_reset(&s->cmd_queue);
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,
+ fifo32_num_free(&s->cmd_queue));
+ uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,
+ CMD_BUF_EMPTY_THLD);
+ if (fifo32_num_free(&s->cmd_queue) >= empty_threshold) {
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1);
+ dw_i3c_update_irq(s);
+ };
+}
+
+static void dw_i3c_resp_queue_reset(DWI3C *s)
+{
+ fifo32_reset(&s->resp_queue);
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /*
+ * This interrupt will always be cleared because the threshold is a minimum
+ * of 1 and the queue size is 0.
+ */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0);
+ dw_i3c_update_irq(s);
+}
+
+static void dw_i3c_ibi_queue_reset(DWI3C *s)
+{
+ fifo32_reset(&s->ibi_queue);
+
+ ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /*
+ * This interrupt will always be cleared because the threshold is a minimum
+ * of 1 and the queue size is 0.
+ */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0);
+ dw_i3c_update_irq(s);
+}
+
+static void dw_i3c_tx_queue_reset(DWI3C *s)
+{
+ fifo32_reset(&s->tx_queue);
+
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,
+ fifo32_num_free(&s->tx_queue));
+ /* TX buf is empty, so this interrupt will always be set. */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1);
+ dw_i3c_update_irq(s);
+}
+
+static void dw_i3c_rx_queue_reset(DWI3C *s)
+{
+ fifo32_reset(&s->rx_queue);
+
+ ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR,
+ fifo32_num_used(&s->resp_queue));
+ /*
+ * This interrupt will always be cleared because the threshold is a minimum
+ * of 1 and the queue size is 0.
+ */
+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0);
+ dw_i3c_update_irq(s);
+}
+
+static void dw_i3c_reset(DeviceState *dev)
+{
+ DWI3C *s = DW_I3C(dev);
+ trace_dw_i3c_reset(s->cfg.id);
+
+ memcpy(s->regs, dw_i3c_resets, sizeof(s->regs));
+ /*
+ * The user config for these may differ from our resets array, set them
+ * manually.
+ */
+ ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR,
+ s->cfg.dev_addr_table_pointer);
+ ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH,
+ s->cfg.dev_addr_table_depth);
+ ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER,
+ P_DEV_CHAR_TABLE_START_ADDR,
+ s->cfg.dev_char_table_pointer);
+ ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,
+ s->cfg.dev_char_table_depth);
+
+ dw_i3c_cmd_queue_reset(s);
+ dw_i3c_resp_queue_reset(s);
+ dw_i3c_ibi_queue_reset(s);
+ dw_i3c_tx_queue_reset(s);
+ dw_i3c_rx_queue_reset(s);
+}
+
+static void dw_i3c_reset_ctrl_w(DWI3C *s, uint32_t val)
+{
+ if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) {
+ dw_i3c_reset(DEVICE(s));
+ }
+ if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) {
+ dw_i3c_cmd_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) {
+ dw_i3c_resp_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) {
+ dw_i3c_tx_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) {
+ dw_i3c_rx_queue_reset(s);
+ }
+ if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) {
+ dw_i3c_ibi_queue_reset(s);
+ }
+}
+
static uint32_t dw_i3c_pop_rx(DWI3C *s)
{
if (fifo32_is_empty(&s->rx_queue)) {
@@ -1617,6 +1733,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
dw_i3c_cmd_queue_port_w(s, val32);
break;
case R_RESET_CTRL:
+ dw_i3c_reset_ctrl_w(s, val32);
break;
case R_INTR_STATUS:
dw_i3c_intr_status_w(s, val32);
diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events
index a262fcce39..39f33d9a50 100644
--- a/hw/i3c/trace-events
+++ b/hw/i3c/trace-events
@@ -11,6 +11,7 @@ dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 "
dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus"
dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8
dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d"
+dw_i3c_reset(uint32_t deviceid) "I3C Dev[%u] reset"
dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO"
dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue"
dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO"
--
2.43.0