[PATCH v7 07/22] hw/i3c/dw-i3c: Add more reset values

Jamin Lin
2026-02-25T02:12:55Z

Adds reset values for the new registers added.

Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/i3c/dw-i3c.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index 48dde008de..28da6016a1 100644
--- a/hw/i3c/dw-i3c.c
+++ b/hw/i3c/dw-i3c.c
@@ -268,14 +268,32 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)

static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
- [R_HW_CAPABILITY] = 0x000e00bf,
+ /* Target mode is not supported, don't advertise it for now. */
+ [R_HW_CAPABILITY] = 0x000e00b9,
[R_QUEUE_THLD_CTRL] = 0x01000101,
+ [R_DATA_BUFFER_THLD_CTRL] = 0x01010100,
+ [R_SLV_EVENT_CTRL] = 0x0000000b,
+ [R_QUEUE_STATUS_LEVEL] = 0x00000002,
+ [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010,
+ [R_PRESENT_STATE] = 0x00000003,
[R_I3C_VER_ID] = 0x3130302a,
[R_I3C_VER_TYPE] = 0x6c633033,
[R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280,
[R_DEV_CHAR_TABLE_POINTER] = 0x00020200,
+ [R_SLV_CHAR_CTRL] = 0x00010000,
[A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
[R_SLV_MAX_LEN] = 0x00ff00ff,
+ [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f,
+ [R_SCL_I3C_OD_TIMING] = 0x000a0010,
+ [R_SCL_I3C_PP_TIMING] = 0x000a000a,
+ [R_SCL_I2C_FM_TIMING] = 0x00100010,
+ [R_SCL_I2C_FMP_TIMING] = 0x00100010,
+ [R_SCL_EXT_LCNT_TIMING] = 0x20202020,
+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000,
+ [R_BUS_FREE_TIMING] = 0x00200020,
+ [R_BUS_IDLE_TIMING] = 0x00000020,
+ [R_EXTENDED_CAPABILITY] = 0x00000239,
+ [R_SLAVE_CONFIG] = 0x00000023,
};

static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
--
2.43.0