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Wed, 8 Jul 2026 09:20:33 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v5 06/10] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers Thread-Topic: [PATCH v5 06/10] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers Thread-Index: AQHdDrsH90codjYdo0iZkdPj6nXDGQ== Date: Wed, 8 Jul 2026 09:20:33 +0000 Message-ID: <20260708092023.3826159-7-jamin_lin@aspeedtech.com> References: <20260708092023.3826159-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260708092023.3826159-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|PUZPR06MB5499:EE_ x-ms-office365-filtering-correlation-id: 37f92a0c-b5a5-479c-d72f-08dedcd229ae x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org This patch implements TSP reset and power control logic in the SCU module= =0A= for AST2700. It introduces support for the following behavior:=0A= =0A= 1. TSP Reset Trigger (via SCU 0x220):=0A= =0A= - TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_= 2.=0A= =0A= 2. TSP Reset State and Source Hold (via SCU 0x160):=0A= =0A= - Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.=0A= - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source.=0A= - Bit 1 (RST) is a software-controlled bit used to request holding TSP i= n reset.=0A= - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB)=0A= will also be asserted to indicate the TSP is being held in reset.=0A= - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.=0A= =0A= 3. Hold Release and Power-on:=0A= =0A= - If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset= is deasserted.=0A= - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_C= TRL_0 to release=0A= the hold and power on TSP explicitly.=0A= - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution.=0A= =0A= 4. Reset Status Clear (via SCU 0x224):=0A= =0A= - The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RS= T_CLR_2,=0A= which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active.=0A= =0A= 5. TSP Power Control Logic:=0A= =0A= - handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and in= vokes=0A= arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).=0A= - handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, als= o asserts=0A= RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).=0A= =0A= The default values are based on EVB (evaluation board) register dump observ= ations.=0A= TSP reset control shares the same helper functions and register bit layout = as SSP,=0A= with logic selected by cpuid and distinct external reset sources.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++-=0A= 1 file changed, 36 insertions(+), 1 deletion(-)=0A= =0A= diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c=0A= index 07901f2ab0..2a20253410 100644=0A= --- a/hw/misc/aspeed_scu.c=0A= +++ b/hw/misc/aspeed_scu.c=0A= @@ -147,6 +147,7 @@=0A= =0A= /* SSP TSP */=0A= #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)=0A= +#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)=0A= #define AST2700_SSP_TSP_ENABLE BIT(0)=0A= #define AST2700_SSP_TSP_RST BIT(1)=0A= #define AST2700_SSP_TSP_RST_RB BIT(8)=0A= @@ -155,6 +156,9 @@=0A= #define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)=0A= #define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)=0A= #define AST2700_SCU_SYS_RST_SSP BIT(30)=0A= +#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)=0A= +#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)=0A= +#define AST2700_SCU_SYS_RST_TSP BIT(9)=0A= =0A= #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)=0A= #define AST2700_SCU_HPLL_PARAM TO_REG(0x300)=0A= @@ -923,7 +927,10 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset,=0A= =0A= switch (reg) {=0A= case AST2700_SCU_SSP_CTRL_0:=0A= - cpuid =3D a->ssp_cpuid;=0A= + case AST2700_SCU_TSP_CTRL_0:=0A= + cpuid =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_0) ?=0A= + a->ssp_cpuid : a->tsp_cpuid;=0A= +=0A= if (cpuid < 0) {=0A= return;=0A= }=0A= @@ -979,6 +986,28 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset,=0A= }=0A= s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active;=0A= return;=0A= + case AST2700_SCU_SYS_RST_CTRL_2:=0A= + if (a->tsp_cpuid < 0) {=0A= + return;=0A= + }=0A= + data &=3D 0x00001fff;=0A= + if (data & AST2700_SCU_SYS_RST_TSP) {=0A= + handle_2700_ssp_tsp_off(s, a->tsp_cpuid, AST2700_SCU_TSP_CTRL_= 0);=0A= + }=0A= + s->regs[reg] |=3D data;=0A= + return;=0A= + case AST2700_SCU_SYS_RST_CLR_2:=0A= + if (a->tsp_cpuid < 0) {=0A= + return;=0A= + }=0A= + data &=3D 0x00001fff;=0A= + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_2];=0A= + active =3D data & oldval;=0A= + if (active & AST2700_SCU_SYS_RST_TSP) {=0A= + handle_2700_ssp_tsp_on(s, a->tsp_cpuid, AST2700_SCU_TSP_CTRL_0= );=0A= + }=0A= + s->regs[AST2700_SCU_SYS_RST_CTRL_2] &=3D ~active;=0A= + return;=0A= default:=0A= qemu_log_mask(LOG_GUEST_ERROR,=0A= "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n"= ,=0A= @@ -1007,7 +1036,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D {=0A= [AST2700_HW_STRAP1_SEC2] =3D 0x00000000,=0A= [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F,=0A= [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE,=0A= + [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE,=0A= [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC,=0A= + [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF,=0A= [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f,=0A= [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f,=0A= [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f,=0A= @@ -1038,6 +1069,10 @@ static void aspeed_ast2700_scu_reset_hold(Object *ob= j, ResetType type)=0A= if (a->ssp_cpuid > 0) {=0A= arm_set_cpu_off(a->ssp_cpuid);=0A= }=0A= +=0A= + if (a->tsp_cpuid > 0) {=0A= + arm_set_cpu_off(a->tsp_cpuid);=0A= + }=0A= }=0A= =0A= static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)=0A= -- =0A= 2.43.0=0A=