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[99.61.67.1]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-66ccafd03basm1986454d50.1.2026.08.19.19.48.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2026 19:48:51 -0700 (PDT) From: Kyle Fox To: qemu-devel@nongnu.org Cc: Kyle Fox , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH 04/16] hw/arm/armv7m: forward pmsav7-rbar-align-down to the CPU Date: Wed, 19 Aug 2026 21:48:22 -0500 Message-Id: <20260820024834.3286721-5-kylefoxaustin.github@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260820024834.3286721-1-kylefoxaustin.github@gmail.com> References: <20260820024834.3286721-1-kylefoxaustin.github@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::112b; envelope-from=kylefoxaustin.github@gmail.com; helo=mail-yw1-x112b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Forward the opt-in "pmsav7-rbar-align-down" property to the CPU object, following the existing init-svtor / vfp / dsp forwarding pattern, so an SoC integrating a PMSAv7 core whose firmware relies on the align-down behaviour can enable it. Signed-off-by: Kyle Fox --- hw/arm/armv7m.c | 8 ++++++++ include/hw/arm/armv7m.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 68a1cbd6316..bb0f95d423d 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -332,6 +332,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } + if (object_property_find(OBJECT(s->cpu), "pmsav7-rbar-align-down")) { + if (!object_property_set_bool(OBJECT(s->cpu), "pmsav7-rbar-align-down", + s->pmsav7_rbar_align_down, errp)) { + return; + } + } object_property_set_bool(OBJECT(s->cpu), "start-powered-off", s->start_powered_off, &error_abort); @@ -562,6 +568,8 @@ static const Property armv7m_properties[] = { false), DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), + DEFINE_PROP_BOOL("pmsav7-rbar-align-down", ARMv7MState, + pmsav7_rbar_align_down, false), DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), }; diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 70555962bb9..23cfed222c1 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -52,6 +52,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object) * + Property "vfp": enable VFP (forwarded to CPU object) * + Property "dsp": enable DSP (forwarded to CPU object) + * + Property "pmsav7-rbar-align-down": align down a misaligned PMSAv7 MPU + * region base rather than treating it as UNPREDICTABLE (forwarded to the + * CPU object, which only offers it on PMSAv7 cores) * + Property "enable-bitband": expose bitbanded IO * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded * to CPU object pmsav7-dregion property; default is whatever the default @@ -108,6 +111,7 @@ struct ARMv7MState { bool start_powered_off; bool vfp; bool dsp; + bool pmsav7_rbar_align_down; }; #endif -- 2.34.1