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Tue, 1 Sep 2026 02:44:02 +0000 From: Jamin Lin To: Paolo Bonzini , Peter Maydell , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , "open list:ARM TCG CPUs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v4 1/4] hw/usb/aspeed-udc: Add ASPEED UDC device controller Thread-Topic: [PATCH v4 1/4] hw/usb/aspeed-udc: Add ASPEED UDC device controller Thread-Index: AQHdObu/DqeJGndzL0iuEikY3pGgyQ== Date: Tue, 1 Sep 2026 02:44:02 +0000 Message-ID: <20260901024400.3488429-2-jamin_lin@aspeedtech.com> References: <20260901024400.3488429-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260901024400.3488429-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|SI4PR06MB8448:EE_ x-ms-office365-filtering-correlation-id: 45477abe-b871-4dd9-9211-08df07d2e215 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The AST2600 has a USB 2.0 Device Controller (UDC) at 0x1e6a2000 with one=0A= control endpoint and four programmable endpoints.=0A= =0A= Add the controller as a sysbus (system) device: the MMIO register map=0A= described with the registerfields macros, the interrupt line and the=0A= soft reset. This is only the register/system side.=0A= =0A= Note: this "device controller" is the system-bus device (TYPE_ASPEED_UDC).= =0A= It is not the gadget USB device (TYPE_ASPEED_UDC_GADGET) that a host=0A= controller enumerates, which is added in the next patch.=0A= =0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= include/hw/usb/aspeed-udc.h | 49 ++++++++=0A= hw/usb/aspeed-udc.c | 236 ++++++++++++++++++++++++++++++++++++=0A= hw/arm/Kconfig | 1 +=0A= hw/usb/Kconfig | 3 +=0A= hw/usb/meson.build | 1 +=0A= hw/usb/trace-events | 7 ++=0A= 6 files changed, 297 insertions(+)=0A= create mode 100644 include/hw/usb/aspeed-udc.h=0A= create mode 100644 hw/usb/aspeed-udc.c=0A= =0A= diff --git a/include/hw/usb/aspeed-udc.h b/include/hw/usb/aspeed-udc.h=0A= new file mode 100644=0A= index 0000000000..58fed5f9a2=0A= --- /dev/null=0A= +++ b/include/hw/usb/aspeed-udc.h=0A= @@ -0,0 +1,49 @@=0A= +/*=0A= + * ASPEED USB Device Controller (UDC)=0A= + *=0A= + * Copyright (c) 2026 ASPEED Technology Inc.=0A= + *=0A= + * SPDX-License-Identifier: GPL-2.0-or-later=0A= + */=0A= +=0A= +#ifndef HW_USB_ASPEED_UDC_H=0A= +#define HW_USB_ASPEED_UDC_H=0A= +=0A= +#include "hw/core/sysbus.h"=0A= +#include "qom/object.h"=0A= +=0A= +#define TYPE_ASPEED_UDC "aspeed.udc"=0A= +OBJECT_DECLARE_SIMPLE_TYPE(AspeedUDCState, ASPEED_UDC)=0A= +=0A= +/*=0A= + * Register map: root/global block at 0x000 - 0x087, then one 0x10 byte ba= nk=0A= + * per programmable endpoint from 0x200.=0A= + */=0A= +#define ASPEED_UDC_MEM_SIZE 0x300=0A= +#define ASPEED_UDC_ROOT_NR_REGS (0x88 >> 2)=0A= +#define ASPEED_UDC_EP_REG_BASE 0x200=0A= +#define ASPEED_UDC_EP_NR_REGS (0x10 >> 2)=0A= +=0A= +/*=0A= + * EP0 (control) is served through the root registers (UDC_EP0_*), so only= =0A= + * the 4 programmable endpoints get their own register bank / ep[] entry.= =0A= + */=0A= +#define ASPEED_UDC_NUM_EP 4=0A= +=0A= +typedef struct AspeedUDCEP {=0A= + MemoryRegion mr;=0A= + uint32_t regs[ASPEED_UDC_EP_NR_REGS];=0A= + int index;=0A= +} AspeedUDCEP;=0A= +=0A= +struct AspeedUDCState {=0A= + SysBusDevice parent_obj;=0A= +=0A= + MemoryRegion udc_container;=0A= + MemoryRegion root_mr;=0A= + uint32_t regs[ASPEED_UDC_ROOT_NR_REGS];=0A= + AspeedUDCEP ep[ASPEED_UDC_NUM_EP];=0A= + qemu_irq irq;=0A= +};=0A= +=0A= +#endif /* HW_USB_ASPEED_UDC_H */=0A= diff --git a/hw/usb/aspeed-udc.c b/hw/usb/aspeed-udc.c=0A= new file mode 100644=0A= index 0000000000..cd773e979b=0A= --- /dev/null=0A= +++ b/hw/usb/aspeed-udc.c=0A= @@ -0,0 +1,236 @@=0A= +/*=0A= + * ASPEED USB Device Controller (UDC)=0A= + *=0A= + * Copyright (c) 2026 ASPEED Technology Inc.=0A= + *=0A= + * SPDX-License-Identifier: GPL-2.0-or-later=0A= + *=0A= + * Models the ASPEED USB Device Controller (UDC). It implements one contro= l=0A= + * endpoint (EP0) and 4 programmable endpoints.=0A= + *=0A= + * This file is the system-bus side of the controller: the MMIO register m= ap,=0A= + * the interrupt and the soft reset. The gadget USB device presented to a = host=0A= + * controller (and the endpoint data path) is added on top of this.=0A= + */=0A= +=0A= +#include "qemu/osdep.h"=0A= +#include "hw/core/irq.h"=0A= +#include "hw/core/registerfields.h"=0A= +#include "hw/usb/aspeed-udc.h"=0A= +#include "qemu/module.h"=0A= +#include "trace.h"=0A= +=0A= +/* Root / Global registers (offset from the controller base) */=0A= +REG32(UDC_FUNC_CTRL, 0x00)=0A= + FIELD(UDC_FUNC_CTRL, UPSTREAM_EN, 0, 1)=0A= +REG32(UDC_IER, 0x08)=0A= +REG32(UDC_ISR, 0x0C)=0A= + FIELD(UDC_ISR, EP_POOL_ACK, 16, 1)=0A= + FIELD(UDC_ISR, BUS_RESET, 6, 1)=0A= + FIELD(UDC_ISR, EP0_IN_ACK, 3, 1)=0A= + FIELD(UDC_ISR, EP0_OUT_ACK, 1, 1)=0A= + FIELD(UDC_ISR, EP0_SETUP, 0, 1)=0A= +REG32(UDC_EP_ACK_IER, 0x10)=0A= +REG32(UDC_EP_NAK_IER, 0x14)=0A= +REG32(UDC_EP_ACK_ISR, 0x18)=0A= +REG32(UDC_EP_NAK_ISR, 0x1C)=0A= +REG32(UDC_DEV_RESET, 0x20)=0A= + FIELD(UDC_DEV_RESET, EP_POOL, 9, 1)=0A= + FIELD(UDC_DEV_RESET, DMA, 8, 1)=0A= + FIELD(UDC_DEV_RESET, ROOT, 0, 1)=0A= +REG32(UDC_STS, 0x24)=0A= + FIELD(UDC_STS, HIGHSPEED, 27, 1)=0A= +REG32(UDC_EP0_CTRL, 0x30)=0A= + FIELD(UDC_EP0_CTRL, RX_LEN, 16, 7)=0A= + FIELD(UDC_EP0_CTRL, TX_LEN, 8, 7)=0A= + FIELD(UDC_EP0_CTRL, RX_RDY, 2, 1)=0A= + FIELD(UDC_EP0_CTRL, TX_RDY, 1, 1)=0A= + FIELD(UDC_EP0_CTRL, STALL, 0, 1)=0A= +REG32(UDC_EP0_DATA_BUFF, 0x34)=0A= +/* EP0 SETUP packet buffer: SETUP0 =3D bytes 0...3, SETUP1 =3D bytes 4...7= */=0A= +REG32(UDC_SETUP0, 0x80)=0A= +REG32(UDC_SETUP1, 0x84)=0A= +=0A= +/* Per programmable-endpoint registers (offset from the EP register base) = */=0A= +REG32(EP_CONFIG, 0x00)=0A= + FIELD(EP_CONFIG, MAX_PKT, 16, 10)=0A= + FIELD(EP_CONFIG, EP_NUM, 8, 4)=0A= + FIELD(EP_CONFIG, DIR_OUT, 4, 1)=0A= + FIELD(EP_CONFIG, ENABLE, 0, 1)=0A= +REG32(EP_DMA_CTRL, 0x04)=0A= + FIELD(EP_DMA_CTRL, PROC_STS, 4, 4)=0A= + FIELD(EP_DMA_CTRL, DESC_OP_EN, 0, 1)=0A= +REG32(EP_DMA_BUFF, 0x08)=0A= +REG32(EP_DMA_STS, 0x0C)=0A= + FIELD(EP_DMA_STS, PKT_SIZE, 16, 11)=0A= + FIELD(EP_DMA_STS, RPTR, 8, 8)=0A= + FIELD(EP_DMA_STS, WPTR, 0, 8)=0A= +=0A= +static void aspeed_udc_update_irq(AspeedUDCState *s)=0A= +{=0A= + bool level;=0A= +=0A= + level =3D (s->regs[R_UDC_ISR] & s->regs[R_UDC_IER]) ||=0A= + (s->regs[R_UDC_EP_ACK_ISR] & s->regs[R_UDC_EP_ACK_IER]) ||=0A= + (s->regs[R_UDC_EP_NAK_ISR] & s->regs[R_UDC_EP_NAK_IER]);=0A= +=0A= + trace_aspeed_udc_irq(s->regs[R_UDC_ISR], s->regs[R_UDC_IER], level);= =0A= + qemu_set_irq(s->irq, level);=0A= +}=0A= +=0A= +static uint64_t aspeed_udc_read(void *opaque, hwaddr offset, unsigned size= )=0A= +{=0A= + AspeedUDCState *s =3D ASPEED_UDC(opaque);=0A= + uint32_t reg =3D offset >> 2;=0A= + uint32_t val;=0A= +=0A= + val =3D s->regs[reg];=0A= + trace_aspeed_udc_read(offset, val);=0A= +=0A= + return val;=0A= +}=0A= +=0A= +static void aspeed_udc_write(void *opaque, hwaddr offset, uint64_t data,= =0A= + unsigned size)=0A= +{=0A= + AspeedUDCState *s =3D ASPEED_UDC(opaque);=0A= + uint32_t reg =3D offset >> 2;=0A= + uint32_t val =3D data;=0A= +=0A= + trace_aspeed_udc_write(offset, val);=0A= +=0A= + switch (reg) {=0A= + case R_UDC_IER:=0A= + case R_UDC_EP_ACK_IER:=0A= + case R_UDC_EP_NAK_IER:=0A= + s->regs[reg] =3D val;=0A= + aspeed_udc_update_irq(s);=0A= + break;=0A= + case R_UDC_ISR:=0A= + case R_UDC_EP_ACK_ISR:=0A= + case R_UDC_EP_NAK_ISR:=0A= + s->regs[reg] &=3D ~val;=0A= + aspeed_udc_update_irq(s);=0A= + break;=0A= + default:=0A= + s->regs[reg] =3D val;=0A= + break;=0A= + }=0A= +}=0A= +=0A= +static const MemoryRegionOps aspeed_udc_ops =3D {=0A= + .read =3D aspeed_udc_read,=0A= + .write =3D aspeed_udc_write,=0A= + .endianness =3D DEVICE_LITTLE_ENDIAN,=0A= + .valid =3D {=0A= + .min_access_size =3D 1,=0A= + .max_access_size =3D 4,=0A= + },=0A= + .impl =3D {=0A= + .min_access_size =3D 4,=0A= + .max_access_size =3D 4,=0A= + },=0A= +};=0A= +=0A= +static uint64_t aspeed_udc_ep_read(void *opaque, hwaddr offset, unsigned s= ize)=0A= +{=0A= + AspeedUDCEP *e =3D opaque;=0A= + uint32_t reg =3D offset >> 2;=0A= + uint32_t val;=0A= +=0A= + val =3D e->regs[reg];=0A= + trace_aspeed_udc_ep_read(e->index, offset, val);=0A= +=0A= + return val;=0A= +}=0A= +=0A= +static void aspeed_udc_ep_write(void *opaque, hwaddr offset, uint64_t data= ,=0A= + unsigned size)=0A= +{=0A= + AspeedUDCEP *e =3D opaque;=0A= + uint32_t reg =3D offset >> 2;=0A= +=0A= + trace_aspeed_udc_ep_write(e->index, offset, data);=0A= + e->regs[reg] =3D data;=0A= +}=0A= +=0A= +static const MemoryRegionOps aspeed_udc_ep_ops =3D {=0A= + .read =3D aspeed_udc_ep_read,=0A= + .write =3D aspeed_udc_ep_write,=0A= + .endianness =3D DEVICE_LITTLE_ENDIAN,=0A= + .valid =3D {=0A= + .min_access_size =3D 1,=0A= + .max_access_size =3D 4,=0A= + },=0A= + .impl =3D {=0A= + .min_access_size =3D 4,=0A= + .max_access_size =3D 4,=0A= + },=0A= +};=0A= +=0A= +static void aspeed_udc_reset_hold(Object *obj, ResetType type)=0A= +{=0A= + AspeedUDCState *s =3D ASPEED_UDC(obj);=0A= + int i;=0A= +=0A= + memset(s->regs, 0, sizeof(s->regs));=0A= + for (i =3D 0; i < ASPEED_UDC_NUM_EP; i++) {=0A= + memset(s->ep[i].regs, 0, sizeof(s->ep[i].regs));=0A= + }=0A= +=0A= + /* Device-reset default: root, DMA and EP-pool soft-reset bits set */= =0A= + s->regs[R_UDC_DEV_RESET] =3D (R_UDC_DEV_RESET_ROOT_MASK |=0A= + R_UDC_DEV_RESET_DMA_MASK |=0A= + R_UDC_DEV_RESET_EP_POOL_MASK);=0A= +}=0A= +=0A= +static void aspeed_udc_realize(DeviceState *dev, Error **errp)=0A= +{=0A= + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev);=0A= + AspeedUDCState *s =3D ASPEED_UDC(dev);=0A= + int i;=0A= +=0A= + memory_region_init(&s->udc_container, OBJECT(s), TYPE_ASPEED_UDC,=0A= + ASPEED_UDC_MEM_SIZE);=0A= + memory_region_init_io(&s->root_mr, OBJECT(s), &aspeed_udc_ops, s,=0A= + TYPE_ASPEED_UDC ".root",=0A= + ASPEED_UDC_ROOT_NR_REGS << 2);=0A= + memory_region_add_subregion(&s->udc_container, 0, &s->root_mr);=0A= +=0A= + /* Each programmable endpoint has its own register bank */=0A= + for (i =3D 0; i < ASPEED_UDC_NUM_EP; i++) {=0A= + g_autofree char *name =3D g_strdup_printf(TYPE_ASPEED_UDC ".ep%d",= i);=0A= +=0A= + s->ep[i].index =3D i;=0A= + memory_region_init_io(&s->ep[i].mr, OBJECT(s), &aspeed_udc_ep_ops,= =0A= + &s->ep[i], name, ASPEED_UDC_EP_NR_REGS << 2)= ;=0A= + memory_region_add_subregion(&s->udc_container,=0A= + ASPEED_UDC_EP_REG_BASE +=0A= + i * (ASPEED_UDC_EP_NR_REGS << 2),=0A= + &s->ep[i].mr);=0A= + }=0A= +=0A= + sysbus_init_mmio(sbd, &s->udc_container);=0A= + sysbus_init_irq(sbd, &s->irq);=0A= +}=0A= +=0A= +static void aspeed_udc_class_init(ObjectClass *klass, const void *data)=0A= +{=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + ResettableClass *rc =3D RESETTABLE_CLASS(klass);=0A= +=0A= + dc->desc =3D "ASPEED USB Device Controller";=0A= + dc->realize =3D aspeed_udc_realize;=0A= + rc->phases.hold =3D aspeed_udc_reset_hold;=0A= +}=0A= +=0A= +static const TypeInfo aspeed_udc_types[] =3D {=0A= + {=0A= + .name =3D TYPE_ASPEED_UDC,=0A= + .parent =3D TYPE_SYS_BUS_DEVICE,=0A= + .instance_size =3D sizeof(AspeedUDCState),=0A= + .class_init =3D aspeed_udc_class_init,=0A= + },=0A= +};=0A= +=0A= +DEFINE_TYPES(aspeed_udc_types)=0A= diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig=0A= index 260d2f0751..146ed1a0be 100644=0A= --- a/hw/arm/Kconfig=0A= +++ b/hw/arm/Kconfig=0A= @@ -536,6 +536,7 @@ config ASPEED_SOC=0A= imply GENERIC_LOADER=0A= imply PCI_DEVICES=0A= imply E1000E_PCI_EXPRESS=0A= + select ASPEED_UDC=0A= select DS1338=0A= select FTGMAC100=0A= select I2C=0A= diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig=0A= index de95686720..e4df15fe7c 100644=0A= --- a/hw/usb/Kconfig=0A= +++ b/hw/usb/Kconfig=0A= @@ -146,3 +146,6 @@ config XLNX_USB_SUBSYS=0A= config USB_CHIPIDEA=0A= bool=0A= select USB_EHCI_SYSBUS=0A= +=0A= +config ASPEED_UDC=0A= + bool=0A= diff --git a/hw/usb/meson.build b/hw/usb/meson.build=0A= index ba55c28ef6..d4ba60a91c 100644=0A= --- a/hw/usb/meson.build=0A= +++ b/hw/usb/meson.build=0A= @@ -27,6 +27,7 @@ system_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files= ('hcd-xhci-nec.c'))=0A= system_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c'))=0A= system_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c'))=0A= system_ss.add(when: 'CONFIG_USB_CHIPIDEA', if_true: files('chipidea.c'))= =0A= +system_ss.add(when: 'CONFIG_ASPEED_UDC', if_true: files('aspeed-udc.c'))= =0A= =0A= system_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c'))= =0A= system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686-uhci-pci.c= '))=0A= diff --git a/hw/usb/trace-events b/hw/usb/trace-events=0A= index 67249d69c2..ed05304520 100644=0A= --- a/hw/usb/trace-events=0A= +++ b/hw/usb/trace-events=0A= @@ -377,3 +377,10 @@ canokey_handle_data_out(uint8_t ep_out, uint32_t out_l= en) "ep %d len %d"=0A= canokey_handle_data_in(uint8_t ep_in, uint32_t in_len) "ep %d len %d"=0A= canokey_realize(void)=0A= canokey_unrealize(void)=0A= +=0A= +# aspeed-udc.c=0A= +aspeed_udc_read(uint64_t offset, uint32_t value) "offset 0x%" PRIx64 " val= ue 0x%x"=0A= +aspeed_udc_write(uint64_t offset, uint32_t value) "offset 0x%" PRIx64 " va= lue 0x%x"=0A= +aspeed_udc_ep_read(int ep, uint64_t offset, uint32_t value) "ep %d, offset= 0x%" PRIx64 " value 0x%x"=0A= +aspeed_udc_ep_write(int ep, uint64_t offset, uint32_t value) "ep %d, offse= t 0x%" PRIx64 " value 0x%x"=0A= +aspeed_udc_irq(uint32_t isr, uint32_t ier, int level) "isr 0x%x, ier 0x%x,= level %d"=0A= -- =0A= 2.53.0=0A=