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From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Phil Dennis-Jordan <phil@philjordan.eu>,
	Alexander Graf <agraf@csgraf.de>,
	Roman Bolshakov <rbolshakov@ddn.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Mohamed Mediouni <mohamed@unpredictable.fr>
Subject: [PATCH 1/3] hvf: arm: advertise ID_AA64PFR0_EL1.GIC
Date: Thu,  3 Sep 2026 06:01:55 +0200	[thread overview]
Message-ID: <20260903040157.74627-2-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20260903040157.74627-1-mohamed@unpredictable.fr>

For the kernel-irqchip=on case, advertise ID_AA64PFR0_EL1.GIC.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
 target/arm/hvf/hvf.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index da3ec521fc..f881d6cc67 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1229,6 +1229,18 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         FIELD_DP64_IDREG(&host_isar, ID_AA64PFR1, SME, 0);
     }
 
+    /*
+     * On HVF, kernel-irqchip implies GICv3.
+     * The kernel-irqchip=off,gic-version=3 legacy case also supports
+     * the host CPU interface but advertising it in ID_AA64PFR0_EL1
+     * is not implemented yet.
+     */
+
+    if (hvf_irqchip_in_kernel()) {
+        /* Advertise the GIC system register interface */
+        FIELD_DP64_IDREG(&host_isar, ID_AA64PFR0, GIC, 1);
+    }
+
     ahcf->isar = host_isar;
 
     /*
-- 
2.54.0 (Apple Git-156)



  reply	other threads:[~2026-09-03  4:02 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-03  4:01 [PATCH 0/3] hvf: arm: add experimental VHE (x-vhe) toggle Mohamed Mediouni
2026-09-03  4:01 ` Mohamed Mediouni [this message]
2026-09-03  4:01 ` [PATCH 2/3] hvf: arm: add experimental VHE toggle Mohamed Mediouni
2026-09-03  4:01 ` [PATCH 3/3] hvf: arm: advertise EL3 support when VHE is on Mohamed Mediouni

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