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envelope-from=bin.meng@processmission.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Instantiate PBR in the E2000 SoC, map its status and boot memories, provide the heterogeneous MPIDR topology, and connect all SoC-owned CPU objects for reset-time handoff. Have the Phytium Pi machine select SD0 and pass its board backend into the SoC. Explicitly reject unsupported -bios and pflash interfaces. Signed-off-by: Bin Meng --- Changes in v2: - Connect PBR to the SoC-owned CPU children - Let the machine configure the SoC-owned PBR backend include/hw/arm/phytium_e2000.h | 11 +++++ hw/arm/phytium_e2000.c | 74 +++++++++++++++++++++++++++++++++- hw/arm/phytium_e2000_machine.c | 26 ++++++++++-- 3 files changed, 107 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/phytium_e2000.h b/include/hw/arm/phytium_e2000.h index 92b39129ba..6199bb7b5c 100644 --- a/include/hw/arm/phytium_e2000.h +++ b/include/hw/arm/phytium_e2000.h @@ -14,6 +14,7 @@ #include "hw/arm/boot.h" #include "hw/core/sysbus.h" +#include "hw/misc/phytium_e2000_pbr.h" #include "hw/net/cadence_gem.h" #include "hw/sd/phytium_e2000_mci.h" #include "hw/ssi/phytium_qspi.h" @@ -67,14 +68,23 @@ struct PhytiumE2000SoCState { DeviceState *gic; PhytiumE2000QSPIState *qspi; + PhytiumE2000PBRState *pbr; PhytiumE2000MciState *mci[PHYTIUM_E2000_NUM_MCIS]; CadenceGEMState *gem[PHYTIUM_E2000_NUM_GEMS]; ARMCPU cpu[PHYTIUM_E2000_NUM_CPUS]; MemoryRegion scp_sram; + + const char *pbr_boot_mode; + BlockBackend *boot_blk; + uint64_t ram_size; unsigned int num_cpus; + bool firmware_loaded; }; void phytium_e2000_soc_configure(PhytiumE2000SoCState *s, + const char *pbr_boot_mode, + BlockBackend *boot_blk, + uint64_t ram_size, unsigned int num_cpus); void phytium_e2000_soc_cpu_topology(unsigned int index, uint64_t *mp_affinity, @@ -82,6 +92,7 @@ void phytium_e2000_soc_cpu_topology(unsigned int index, int64_t *core_id); ARMCPU *phytium_e2000_soc_cpu(PhytiumE2000SoCState *s, unsigned int index); +bool phytium_e2000_soc_firmware_loaded(PhytiumE2000SoCState *s); void phytium_e2000_soc_attach_sd_card(PhytiumE2000SoCState *s, unsigned int index, BlockBackend *blk); diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index 3e30d112f7..6818d081b3 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -23,6 +23,7 @@ #include "hw/intc/arm_gicv3_its_common.h" #include "hw/misc/phytium_e2000_ddr.h" #include "hw/misc/phytium_e2000_mhu.h" +#include "hw/misc/phytium_e2000_pbr.h" #include "hw/misc/unimp.h" #include "hw/net/cadence_gem.h" #include "hw/pci/pci.h" @@ -224,6 +225,17 @@ static void phytium_e2000_configure_cpu(ARMCPU *cpu, } } +static uint64_t phytium_e2000_cpu_mp_affinity(unsigned int cpu) +{ + /* + * E2000Q exposes one core in each of the first two clusters and two cores + * in the third cluster. Firmware stores these MPIDRs in its parameter + * tables, so a linear CPU index is not a valid affinity value. + */ + g_assert(cpu < ARRAY_SIZE(phytium_e2000_cpu_config)); + return phytium_e2000_cpu_config[cpu].mp_affinity; +} + static void phytium_e2000_create_its(PhytiumE2000SoCState *s) { DeviceState *dev = qdev_new(its_class_name()); @@ -483,6 +495,39 @@ static void phytium_e2000_create_qspi(PhytiumE2000SoCState *s) phytium_e2000_memmap[PHYTIUM_E2000_QSPI_DIRECT].base, 2); } +static bool phytium_e2000_create_pbr(PhytiumE2000SoCState *s) +{ + DeviceState *dev = qdev_new(TYPE_PHYTIUM_E2000_PBR); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + uint64_t cpu_mpidrs[PHYTIUM_E2000_NUM_CPUS]; + int i; + + for (i = 0; i < s->num_cpus; i++) { + cpu_mpidrs[i] = phytium_e2000_cpu_mp_affinity(i); + } + + qdev_prop_set_string(dev, "boot-mode", s->pbr_boot_mode); + phytium_e2000_pbr_configure(PHYTIUM_E2000_PBR(dev), s->boot_blk, + phytium_e2000_memmap[PHYTIUM_E2000_RAM].base, + s->ram_size, cpu_mpidrs, s->num_cpus); + + /* + * PBR owns the status snapshot and both boot memories. The status block + * overlaps the broad board-control placeholder and therefore needs the + * higher mapping priority used by the previous status-only device. + */ + object_property_add_child(OBJECT(s), "pbr", OBJECT(dev)); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map_overlap(sbd, 0, PHYTIUM_E2000_PBR_STATUS_BASE, 2); + sysbus_mmio_map(sbd, 1, + phytium_e2000_memmap[PHYTIUM_E2000_BOOT_SRAM].base); + sysbus_mmio_map(sbd, 2, + phytium_e2000_memmap[PHYTIUM_E2000_BOOT_IACC].base); + s->pbr = PHYTIUM_E2000_PBR(dev); + + return phytium_e2000_pbr_firmware_loaded(s->pbr); +} + static void phytium_e2000_create_ddr_status(PhytiumE2000SoCState *s) { DeviceState *dev = qdev_new(TYPE_PHYTIUM_E2000_DDR); @@ -572,23 +617,40 @@ static void phytium_e2000_create_cpus(PhytiumE2000SoCState *s) config->mp_affinity, &error_abort); object_property_set_int(cpuobj, "cntfrq", PHYTIUM_E2000_GTIMER_HZ, &error_abort); - if (object_property_find(cpuobj, "has_el3")) { + if (!s->firmware_loaded && object_property_find(cpuobj, "has_el3")) { /* * The generic-loader U-Boot path starts after the EL3 firmware * stages that normally provide the Phytium SMC services. */ object_property_set_bool(cpuobj, "has_el3", false, &error_abort); } + /* + * PBR releases only the primary MPIDR named in the firmware parameter + * header. Secondary CPUs remain powered off for later firmware or + * PSCI bring-up. + */ + if (s->firmware_loaded && + i != phytium_e2000_pbr_primary_cpu(s->pbr)) { + object_property_set_bool(cpuobj, "start-powered-off", true, + &error_abort); + } object_property_set_link(cpuobj, "memory", OBJECT(get_system_memory()), &error_abort); cs->cpu_index = i; qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); + phytium_e2000_pbr_connect_cpu(s->pbr, i, cs); } } void phytium_e2000_soc_configure(PhytiumE2000SoCState *s, + const char *pbr_boot_mode, + BlockBackend *boot_blk, + uint64_t ram_size, unsigned int num_cpus) { + s->pbr_boot_mode = pbr_boot_mode; + s->boot_blk = boot_blk; + s->ram_size = ram_size; s->num_cpus = num_cpus; } @@ -613,6 +675,11 @@ ARMCPU *phytium_e2000_soc_cpu(PhytiumE2000SoCState *s, return &s->cpu[index]; } +bool phytium_e2000_soc_firmware_loaded(PhytiumE2000SoCState *s) +{ + return s->firmware_loaded; +} + void phytium_e2000_soc_attach_sd_card(PhytiumE2000SoCState *s, unsigned int index, BlockBackend *blk) @@ -643,9 +710,14 @@ static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp) PHYTIUM_E2000_NUM_CPUS); return; } + if (!s->pbr_boot_mode) { + error_setg(errp, "E2000 SoC boot mode is not configured"); + return; + } phytium_e2000_create_unimplemented(s); phytium_e2000_create_qspi(s); + s->firmware_loaded = phytium_e2000_create_pbr(s); phytium_e2000_create_cpus(s); phytium_e2000_create_gic(s); diff --git a/hw/arm/phytium_e2000_machine.c b/hw/arm/phytium_e2000_machine.c index 7397c58a78..3ab82c5fff 100644 --- a/hw/arm/phytium_e2000_machine.c +++ b/hw/arm/phytium_e2000_machine.c @@ -53,6 +53,15 @@ static void phytium_e2000_attach_sd_cards(PhytiumPiMachineState *s) } } +static void phytium_e2000_reject_legacy_firmware(MachineState *ms) +{ + if (ms->firmware || drive_get(IF_PFLASH, 0, 0)) { + error_report("phytium-pi: -bios and pflash firmware are not " + "supported; use an if=sd,index=0 image"); + exit(1); + } +} + static void phytium_e2000_create_ram(PhytiumPiMachineState *s) { MachineState *ms = MACHINE(s); @@ -83,6 +92,8 @@ static void phytium_e2000_create_ram(PhytiumPiMachineState *s) static void phytium_pi_init(MachineState *ms) { PhytiumPiMachineState *s = PHYTIUM_PI(ms); + BlockBackend *boot_blk; + bool firmware_loaded; /* * KVM cannot provide the heterogeneous FTC CPU configuration applied to @@ -107,20 +118,25 @@ static void phytium_pi_init(MachineState *ms) exit(1); } + phytium_e2000_reject_legacy_firmware(ms); phytium_e2000_create_ram(s); + boot_blk = ms->kernel_filename ? NULL : phytium_e2000_sd_blk(0); object_initialize_child(OBJECT(s), "soc", &s->soc, TYPE_PHYTIUM_E2000_SOC); - phytium_e2000_soc_configure(&s->soc, ms->smp.cpus); + phytium_e2000_soc_configure(&s->soc, + PHYTIUM_E2000_PBR_BOOT_MODE_SD0, + boot_blk, ms->ram_size, ms->smp.cpus); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); phytium_e2000_attach_sd_cards(s); + firmware_loaded = phytium_e2000_soc_firmware_loaded(&s->soc); s->bootinfo.ram_size = ms->ram_size; s->bootinfo.board_id = -1; s->bootinfo.loader_start = phytium_e2000_memmap[PHYTIUM_E2000_RAM].base; s->bootinfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; - s->bootinfo.firmware_loaded = false; + s->bootinfo.firmware_loaded = firmware_loaded; arm_load_kernel(phytium_e2000_soc_cpu(&s->soc, 0), ms, &s->bootinfo); } @@ -167,7 +183,11 @@ static void phytium_pi_class_init(ObjectClass *oc, const void *data) mc->valid_cpu_types = valid_cpu_types; mc->max_cpus = PHYTIUM_E2000_NUM_CPUS; mc->default_cpus = PHYTIUM_E2000_NUM_CPUS; - mc->default_ram_size = 1 * GiB; + /* + * PBF/BL1 relocates to 0xf8c40000, which is outside a 1 GiB RAM window + * starting at 0x80000000. Two GiB is the minimum useful firmware default. + */ + mc->default_ram_size = 2 * GiB; mc->default_ram_id = "phytium-e2000.ram"; mc->minimum_page_bits = 12; mc->block_default_type = IF_SD; -- 2.53.0