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envelope-from=bin.meng@processmission.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Instantiate all four standard Cadence GEM controllers described by the E2000 SoC device tree. The generic model implements the first 0x800 bytes of each 0x2000-byte E2000 aperture, so cover the complete window with a low-priority unimplemented region and map the Cadence registers on top. This accepts accesses to the SoC-specific clock and SerDes selectors without inventing their behavior. Connect eight queue interrupts for GEM0 and four for GEM1 through GEM3, and configure the PCS, MDIO PHY address and 16360-byte jumbo limit expected by the SDK drivers. Signed-off-by: Bin Meng --- Changes in v2: - Move GEM controllers and placeholder regions into the E2000 SoC include/hw/arm/phytium_e2000.h | 7 ++++ hw/arm/phytium_e2000.c | 59 ++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + 3 files changed, 67 insertions(+) diff --git a/include/hw/arm/phytium_e2000.h b/include/hw/arm/phytium_e2000.h index e759d71746..a948c54f2c 100644 --- a/include/hw/arm/phytium_e2000.h +++ b/include/hw/arm/phytium_e2000.h @@ -14,6 +14,7 @@ #include "hw/arm/boot.h" #include "hw/core/sysbus.h" +#include "hw/net/cadence_gem.h" #include "hw/sd/phytium_e2000_mci.h" #include "qemu/typedefs.h" #include "target/arm/cpu.h" @@ -23,6 +24,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PhytiumE2000SoCState, PHYTIUM_E2000_SOC) #define PHYTIUM_E2000_NUM_CPUS 4 #define PHYTIUM_E2000_NUM_MCIS 2 +#define PHYTIUM_E2000_NUM_GEMS 4 enum { PHYTIUM_E2000_LOW_PERIPH, @@ -42,6 +44,10 @@ enum { PHYTIUM_E2000_PCIE_CTRL, PHYTIUM_E2000_PCIE_PHY_CTRL, PHYTIUM_E2000_BOARD_CTRL, + PHYTIUM_E2000_GEM0, + PHYTIUM_E2000_GEM1, + PHYTIUM_E2000_GEM2, + PHYTIUM_E2000_GEM3, PHYTIUM_E2000_BOOT_IACC, PHYTIUM_E2000_PCIE_ECAM, PHYTIUM_E2000_PCIE_PIO, @@ -58,6 +64,7 @@ struct PhytiumE2000SoCState { DeviceState *gic; PhytiumE2000MciState *mci[PHYTIUM_E2000_NUM_MCIS]; + CadenceGEMState *gem[PHYTIUM_E2000_NUM_GEMS]; ARMCPU cpu[PHYTIUM_E2000_NUM_CPUS]; unsigned int num_cpus; }; diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index c618065ffe..da8313d61f 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -22,9 +22,11 @@ #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/misc/unimp.h" +#include "hw/net/cadence_gem.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/sd/sd.h" +#include "net/net.h" #include "qobject/qlist.h" #include "qom/object.h" #include "target/arm/cpu.h" @@ -62,6 +64,10 @@ const MemMapEntry phytium_e2000_memmap[] = { [PHYTIUM_E2000_PCIE_CTRL] = { 0x31000000, 0x00200000 }, [PHYTIUM_E2000_PCIE_PHY_CTRL] = { 0x31500000, 0x00001000 }, [PHYTIUM_E2000_BOARD_CTRL] = { 0x31800000, 0x01400000 }, + [PHYTIUM_E2000_GEM0] = { 0x3200c000, 0x00002000 }, + [PHYTIUM_E2000_GEM1] = { 0x3200e000, 0x00002000 }, + [PHYTIUM_E2000_GEM2] = { 0x32010000, 0x00002000 }, + [PHYTIUM_E2000_GEM3] = { 0x32012000, 0x00002000 }, [PHYTIUM_E2000_BOOT_IACC] = { 0x38000000, 0x08000000 }, [PHYTIUM_E2000_PCIE_ECAM] = { 0x40000000, 0x10000000 }, [PHYTIUM_E2000_PCIE_PIO] = { 0x50000000, 0x00f00000 }, @@ -86,6 +92,16 @@ static const int phytium_e2000_uart_irqmap[] = { [6] = 107, }; +static const uint8_t phytium_e2000_gem_num_queues[] = { 8, 4, 4, 4 }; + +static const int +phytium_e2000_gem_irqmap[PHYTIUM_E2000_NUM_GEMS][MAX_PRIORITY_QUEUES] = { + [0] = { 55, 56, 57, 58, 28, 29, 30, 31 }, + [1] = { 59, 60, 61, 62 }, + [2] = { 64, 65, 66, 67 }, + [3] = { 68, 69, 70, 71 }, +}; + static const int phytium_e2000_pcie_irqmap[PCI_NUM_PINS] = { [0] = 4, [1] = 5, @@ -298,6 +314,45 @@ static void phytium_e2000_create_unimplemented_region( phytium_e2000_memmap[map_idx].base, -1000); } +static void phytium_e2000_create_gem(PhytiumE2000SoCState *s, int index) +{ + DeviceState *dev = qdev_new(TYPE_CADENCE_GEM); + CadenceGEMState *gem = CADENCE_GEM(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + g_autofree char *name = g_strdup_printf("gem%d", index); + g_autofree char *unimp_child = + g_strdup_printf("gem%d-unimplemented", index); + g_autofree char *unimp_name = + g_strdup_printf("phytium-e2000.gem%d-unimplemented", index); + int map_idx = PHYTIUM_E2000_GEM0 + index; + hwaddr base = phytium_e2000_memmap[map_idx].base; + int i; + + s->gem[index] = gem; + object_property_add_child(OBJECT(s), name, OBJECT(dev)); + + qemu_configure_nic_device(dev, true, name); + qdev_prop_set_uint8(dev, "phy-addr", 0); + qdev_prop_set_uint8(dev, "num-priority-queues", + phytium_e2000_gem_num_queues[index]); + qdev_prop_set_uint16(dev, "jumbo-max-len", 16360); + qdev_prop_set_bit(dev, "pcs-enabled", true); + + /* + * The E2000 exposes a 0x2000-byte aperture, while the generic Cadence + * model implements the first 0x800 bytes. Catch accesses to the remaining + * SoC-specific registers without inventing their clock and SerDes effects. + */ + phytium_e2000_create_unimplemented_region( + s, unimp_child, unimp_name, map_idx); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + for (i = 0; i < phytium_e2000_gem_num_queues[index]; i++) { + sysbus_connect_irq(sbd, i, + qdev_get_gpio_in(s->gic, phytium_e2000_gem_irqmap[index][i])); + } +} + /* The vendor DT maps root-bus INTx solely by pin */ static int phytium_e2000_pcie_map_irq(PCIDevice *pdev, int pin) { @@ -535,6 +590,10 @@ static void phytium_e2000_soc_realize(DeviceState *dev, Error **errp) for (i = 0; i < PHYTIUM_E2000_NUM_UARTS; i++) { phytium_e2000_create_uart(s, i); } + for (i = 0; i < PHYTIUM_E2000_NUM_GEMS; i++) { + phytium_e2000_create_gem(s, i); + } + phytium_e2000_create_pcie(s); } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8b865e4e30..d9759731f0 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -132,6 +132,7 @@ config PHYTIUM_E2000 depends on TCG && AARCH64 imply PCI_DEVICES select ARM_GIC + select CADENCE select DW_MCI select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE -- 2.53.0