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([2001:8003:3a49:fd00:e4a0:3bb7:a616:35c9]) by smtp.gmail.com with ESMTPSA id z13sm8229pfh.45.2022.02.03.14.02.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Feb 2022 14:02:21 -0800 (PST) Message-ID: <2b1358f1-0447-4805-d7e2-e01eb1b3ed9d@linaro.org> Date: Fri, 4 Feb 2022 09:02:16 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 06/13] hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite() Content-Language: en-US To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , Shashi Mallela References: <20220201193207.2771604-1-peter.maydell@linaro.org> <20220201193207.2771604-7-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TUID: bDCCVj5fG7L9 On 2/3/22 21:45, Peter Maydell wrote: > On Thu, 3 Feb 2022 at 03:59, Richard Henderson > wrote: >> >> On 2/2/22 06:32, Peter Maydell wrote: >>> In get_ite() and update_ite() we work with a 12-byte in-guest-memory >>> table entry, which we intend to handle as an 8-byte value followed by >>> a 4-byte value. Unfortunately the calculation of the address of the >>> 4-byte value is wrong, because we write it as: >>> >>> table_base_address + (index * entrysize) + 4 >>> (obfuscated by the way the expression has been written) >>> >>> when it should be + 8. This bug meant that we overwrote the top >>> bytes of the 8-byte value with the 4-byte value. There are no >>> guest-visible effects because the top half of the 8-byte value >>> contains only the doorbell interrupt field, which is used only in >>> GICv4, and the two bugs in the "write ITE" and "read ITE" codepaths >>> cancel each other out. >>> >>> We can't simply change the calculation, because this would break >>> migration of a (TCG) guest from the old version of QEMU which had >>> in-guest-memory interrupt tables written using the buggy version of >>> update_ite(). We must also at the same time change the layout of the >>> fields within the ITE_L and ITE_H values so that the in-memory >>> locations of the fields we care about (VALID, INTTYPE, INTID and >>> ICID) stay the same. > >> This is confusing: 5-3 is titled "example of the number of bits that might be stored in an >> ITE"? Surely there must be a true architected format for this table, the one real >> hardware uses. Surely tcg will simply have to suck it up and break migration to fix this >> properly. > > No, the ITE format is implementation-defined, like that of the other > in-guest-memory tables the ITS uses. It's UNPREDICTABLE for a guest > to try to directly access the tables in memory -- they are only ever > written or read by the ITS itself in response to incoming commands, > so it's not a problem for the format in memory to be impdef. This > flexibility in the spec allows implementations to minimize the size > of their data tables based on how large an ID size they support and > other potentially-configurable parameters. For instance if you look > at the values for the GITS_BASER* for the GIC-700 in its TRM you > can see that its Collection Table entry size is only 2 bytes, since > it uses the "rdbase is a CPU number" format; an ITS that used the > "rdbase is a physical address" implementation choice would need > more bytes there. (QEMU also uses "rdbase is a CPU number", but > we have rather profligately opted to use 8 bytes per collection > table entry.) Ah, right. In which case, Reviewed-by: Richard Henderson r~