From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] target/arm: Don't set HCR.RW for AArch32 only CPUs
Date: Thu, 25 Sep 2025 15:29:32 +0200 [thread overview]
Message-ID: <2bab9ba5-263b-466f-8748-3d65a1d8d93c@linaro.org> (raw)
In-Reply-To: <20250925115723.1293233-1-peter.maydell@linaro.org>
On 25/9/25 13:57, Peter Maydell wrote:
> In commit 39ec3fc0301 we fixed a bug where we were not implementing
> HCR_EL2.RW as RAO/WI for CPUs where EL1 doesn't support AArch32.
> However, we got the condition wrong, so we now set this bit even on
> CPUs which have no AArch64 support at all. This is wrong because the
> AArch32 HCR register defines this bit as RES0.
>
> Correct the condition we use for forcing HCR_RW to be set.
>
> Cc: qemu-stable@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3128
> Fixes: 39ec3fc0301 ("target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
prev parent reply other threads:[~2025-09-25 13:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 11:57 [PATCH] target/arm: Don't set HCR.RW for AArch32 only CPUs Peter Maydell
2025-09-25 13:29 ` Philippe Mathieu-Daudé [this message]
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