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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4773c383c20sm225733445e9.12.2025.11.04.08.01.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Nov 2025 08:01:58 -0800 (PST) Message-ID: <3c9e00f5-de9e-4e5c-8312-75eb4fcef81b@redhat.com> Date: Tue, 4 Nov 2025 17:01:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 15/32] hw/pci/pci: Introduce optional get_msi_address_space() callback To: Shameer Kolothum , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-16-skolothumtho@nvidia.com> <318947de-4467-4ced-a5d2-929e3df210ef@redhat.com> <85f315a2-e49a-4330-9419-48a8a3a4a3e3@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: gXcJ74_1bgLsn34D4E93CyUBxmxvhINo0NdwLUP6300_1762272120 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.788, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 11/4/25 4:14 PM, Shameer Kolothum wrote: > >> -----Original Message----- >> From: Eric Auger >> Sent: 04 November 2025 14:44 >> To: Shameer Kolothum ; qemu- >> arm@nongnu.org; qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; Jason Gunthorpe ; Nicolin >> Chen ; ddutile@redhat.com; berrange@redhat.com; >> Nathan Chen ; Matt Ochs ; >> smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >> zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; yi.l.liu@intel.com; >> Krishnakant Jaju >> Subject: Re: [PATCH v5 15/32] hw/pci/pci: Introduce optional >> get_msi_address_space() callback >> >> External email: Use caution opening links or attachments >> >> >> On 11/4/25 3:37 PM, Shameer Kolothum wrote: >>> Hi Eric, >>> >>>> -----Original Message----- >>>> From: Eric Auger >>>> Sent: 04 November 2025 14:12 >>>> To: Shameer Kolothum ; qemu- >>>> arm@nongnu.org; qemu-devel@nongnu.org >>>> Cc: peter.maydell@linaro.org; Jason Gunthorpe ; Nicolin >>>> Chen ; ddutile@redhat.com; berrange@redhat.com; >>>> Nathan Chen ; Matt Ochs ; >>>> smostafa@google.com; wangzhou1@hisilicon.com; >>>> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >>>> zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; yi.l.liu@intel.com; >>>> Krishnakant Jaju >>>> Subject: Re: [PATCH v5 15/32] hw/pci/pci: Introduce optional >>>> get_msi_address_space() callback >>>> >>>> External email: Use caution opening links or attachments >>>> >>>> >>>> Hi Shameer, Nicolin, >>>> >>>> On 10/31/25 11:49 AM, Shameer Kolothum wrote: >>>>> On ARM, devices behind an IOMMU have their MSI doorbell addresses >>>>> translated by the IOMMU. In nested mode, this translation happens in >>>>> two stages (gIOVA → gPA → ITS page). >>>>> >>>>> In accelerated SMMUv3 mode, both stages are handled by hardware, so >>>>> get_address_space() returns the system address space so that VFIO >>>>> can setup stage-2 mappings for system address space. >>>> Sorry but I still don't catch the above. Can you explain (most probably >>>> again) why this is a requirement to return the system as so that VFIO >>>> can setup stage-2 mappings for system address space. I am sorry for >>>> insisting (at the risk of being stubborn or dumb) but I fail to >>>> understand the requirement. As far as I remember the way I integrated it >>>> at the old times did not require that change: >>>> https://lore.kernel.org/all/20210411120912.15770-1- >>>> eric.auger@redhat.com/ >>>> I used a vfio_prereg_listener to force the S2 mapping. >>> Yes I remember that. >>> >>>> What has changed that forces us now to have this gym >>> This approach achieves the same outcome, but through a >>> different mechanism. Returning the system address space >>> here ensures that VFIO sets up the Stage-2 mappings for >>> devices behind the accelerated SMMUv3. >>> >>> I think, this makes sense because, in the accelerated case, the >>> device is no longer managed by QEMU’s SMMUv3 model. The >> On the other hand, as we discussed on v4 by returning system as you >> pretend there is no translation in place which is not true. Now we use >> an alias for it but it has not really removed its usage. Also it forces >> use to hack around the MSI mapping and introduce new PCIIOMMUOps. >> Have >> you assessed the feasability of using vfio_prereg_listener to force the >> S2 mapping. Is it simply not relevant anymore or could it be used also >> with the iommufd be integration? Eric > IIUC, the prereg_listener mechanism just enables us to setup the s2 > mappings. For MSI, In your version, I see that smmu_find_add_as() > always returns IOMMU as. How is that supposed to work if the Guest > has s1 bypass mode STE for the device? I need to delve into it again as I forgot the details. Will come back to you ... Eric > > Thanks, > Shameer > >