Re: [PATCH v2 2/2] target/arm: Implement ID_AA64PFR2_EL1

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 23/9/25 19:57, Peter Maydell wrote:
> Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with
> the required RAZ behaviour for unassigned system registers in the ID
> register encoding space).  Newer architecture versions start to
> define fields in this ID register, so define the appropriate
> constants and implement it as an ID register backed by a field in
> cpu->isar.  Since none of our CPUs set that isar field to non-zero,
> there is no behavioural change here (other than the name exposed to
> the user via the gdbstub), but this paves the way for implementing
> the new features that use fields in this register.
> 
> The fields here are the ones documented in rev L.b of the Arm ARM.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/cpu-features.h    | 5 +++++
>   target/arm/cpu-sysregs.h.inc | 1 +
>   target/arm/helper.c          | 6 ++++--
>   target/arm/hvf/hvf.c         | 2 ++
>   target/arm/kvm.c             | 1 +
>   5 files changed, 13 insertions(+), 2 deletions(-)

To the best of my knowledge,

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>