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[80.11.198.90]) by smtp.googlemail.com with ESMTPSA id l67sm1969885wmf.11.2016.01.28.01.39.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Jan 2016 01:39:17 -0800 (PST) To: Pavel Fedin , eric.auger@st.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.williamson@redhat.com, pranav.sawargaonkar@gmail.com, pbonzini@redhat.com, agraf@suse.de References: <1453902715-25304-1-git-send-email-eric.auger@linaro.org> <1453902715-25304-7-git-send-email-eric.auger@linaro.org> <00a901d1599a$eba575a0$c2f060e0$@samsung.com> From: Eric Auger Message-ID: <56A9E1B4.2000608@linaro.org> Date: Thu, 28 Jan 2016 10:39:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <00a901d1599a$eba575a0$c2f060e0$@samsung.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::229 Cc: Bharat.Bhushan@freescale.com, suravee.suthikulpanit@amd.com, christoffer.dall@linaro.org Subject: Re: [Qemu-arm] [RFC 6/7] hw: arm: virt: register reserved IOVA region X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: fGf9qsThpCYc Hi Pavel, On 01/28/2016 08:10 AM, Pavel Fedin wrote: > Hello! > >> diff --git a/hw/arm/virt.c b/hw/arm/virt.c >> index 3839c68..7eaf8be 100644 >> --- a/hw/arm/virt.c >> +++ b/hw/arm/virt.c >> @@ -125,6 +125,7 @@ static const MemMapEntry a15memmap[] = { >> [VIRT_GPIO] = { 0x09030000, 0x00001000 }, >> [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, >> [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, >> + [VIRT_RESERVED] = { 0x0be00000, 0x00100000 }, > > Looks like with this approach we would need to add this to all machine models which make use of PCI. But is it a good idea? Yes that's correct. On the other hand not all platforms do need that feature. As far > as i understand, the only requirement for this region is not to clash with guest RAM addresses. So, can we instead have some code, > which automatically finds some place, based on the size? Maybe we could use the IOVA region already reserved for platform bus which is currently sparsely used (by vfio platform devices). For now we hardcode the size to 0x00100000, but in future we could query > the host for the size, because it's still host's MSI controller. Yes I agree, this is something we currently miss. I need to study how we can go through all domains/groups and get the max number of MSI frames used by any. Thanks for the follow-up! Regards Eric > > Kind regards, > Pavel Fedin > Senior Engineer > Samsung Electronics Research center Russia > >