From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
qemu-arm@nongnu.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 7/8] target-arm: Implement remaining illegal return event checks
Date: Fri, 29 Jan 2016 19:47:51 +0300 [thread overview]
Message-ID: <56AB97B7.4040301@gmail.com> (raw)
In-Reply-To: <1452796451-2946-8-git-send-email-peter.maydell@linaro.org>
On 14.01.2016 21:34, Peter Maydell wrote:
> We already implement almost all the checks for the illegal
> return events from AArch64 state described in the ARM ARM section
> D1.11.2. Add the two missing ones:
> * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0
> * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1
>
> (We don't implement external debug, so the case of "debug state exit
> from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply
> for QEMU.)
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/op_helper.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 38d46d8..5789ccb 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -718,6 +718,17 @@ void HELPER(exception_return)(CPUARMState *env)
> goto illegal_return;
> }
>
> + if (new_el == 2 && arm_is_secure_below_el3(env)) {
> + /* Return to the non-existent secure-EL2 */
> + goto illegal_return;
> + }
> +
> + if (new_el == 1 &&
> + arm_feature(env, ARM_FEATURE_EL2) && (env->cp15.hcr_el2 & HCR_TGE)
> + && !arm_is_secure_below_el3(env)) {
> + goto illegal_return;
> + }
> +
> if (!return_to_aa64) {
> env->aarch64 = 0;
> env->uncached_cpsr = spsr & CPSR_M;
next prev parent reply other threads:[~2016-01-29 16:47 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-14 18:34 [PATCH 0/8] target-arm: support mixed 32/64 bit execution beyond EL0 Peter Maydell
2016-01-14 18:34 ` [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() Peter Maydell
2016-01-15 14:38 ` Edgar E. Iglesias
2016-01-15 14:50 ` Peter Maydell
2016-01-15 15:37 ` Edgar E. Iglesias
2016-01-15 15:47 ` Peter Maydell
2016-01-15 20:37 ` Edgar E. Iglesias
2016-01-29 16:45 ` [Qemu-devel] " Sergey Fedorov
2016-01-29 16:50 ` Sergey Fedorov
2016-01-29 17:05 ` Peter Maydell
2016-01-29 17:08 ` Sergey Fedorov
2016-01-14 18:34 ` [PATCH 2/8] target-arm: Move aarch64_cpu_do_interrupt() to helper.c Peter Maydell
2016-01-15 14:39 ` Edgar E. Iglesias
2016-01-29 16:46 ` [Qemu-devel] " Sergey Fedorov
2016-01-14 18:34 ` [PATCH 3/8] target-arm: Use a single entry point for AArch64 and AArch32 exceptions Peter Maydell
2016-01-15 14:54 ` Edgar E. Iglesias
2016-01-29 16:46 ` [Qemu-arm] " Sergey Fedorov
2016-01-14 18:34 ` [PATCH 4/8] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() Peter Maydell
2016-01-29 16:46 ` [Qemu-devel] " Sergey Fedorov
2016-01-14 18:34 ` [PATCH 5/8] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target Peter Maydell
2016-01-19 16:40 ` Edgar E. Iglesias
2016-01-29 16:47 ` [Qemu-devel] " Sergey Fedorov
2016-01-14 18:34 ` [PATCH 6/8] target-arm: Handle exception return from AArch64 to non-EL0 AArch32 Peter Maydell
2016-01-19 16:47 ` Edgar E. Iglesias
2016-01-29 16:47 ` [Qemu-arm] " Sergey Fedorov
2016-01-14 18:34 ` [PATCH 7/8] target-arm: Implement remaining illegal return event checks Peter Maydell
2016-01-19 16:53 ` Edgar E. Iglesias
2016-01-19 16:58 ` Peter Maydell
2016-01-29 16:47 ` Sergey Fedorov [this message]
2016-01-14 18:34 ` [PATCH 8/8] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode Peter Maydell
2016-01-19 16:56 ` Edgar E. Iglesias
2016-01-29 16:48 ` [Qemu-devel] [Qemu-arm] " Sergey Fedorov
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