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[46.188.121.154]) by smtp.googlemail.com with ESMTPSA id g74sm1793622lfi.1.2016.02.12.01.34.46 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 12 Feb 2016 01:34:46 -0800 (PST) To: Peter Maydell , qemu-devel@nongnu.org References: <1455217909-28317-1-git-send-email-peter.maydell@linaro.org> <1455217909-28317-5-git-send-email-peter.maydell@linaro.org> From: Sergey Fedorov Message-ID: <56BDA736.3070008@gmail.com> Date: Fri, 12 Feb 2016 12:34:46 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1455217909-28317-5-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c04::242 Cc: qemu-arm@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 2g6WAQFlnEll On 11.02.2016 22:11, Peter Maydell wrote: > Make get_r13_banked() raise an exception at runtime for the > corner case of SRS from System mode, so that we can UNDEF it; > this brings us in to line with the ARM ARM's set of permitted > CONSTRAINED UNPREDICTABLE choices. > > Signed-off-by: Peter Maydell It's a bit misleading that the name "get_r13_banked" says nothing about SRS instruction but raises an SRS-specific exception. Though, it's only used for SRS and there seems to be no other candidate to use it; so Reviewed-by: Sergey Fedorov > --- > target-arm/op_helper.c | 8 ++++++++ > target-arm/translate.c | 9 +++++---- > 2 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 05f97a7..8183108 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -474,6 +474,14 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) > #if defined(CONFIG_USER_ONLY) > g_assert_not_reached(); > #endif > + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { > + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. > + * Other UNPREDICTABLE and UNDEF cases were caught at translate time. > + */ > + raise_exception(env, EXCP_UDEF, syn_uncategorized(), > + exception_target_el(env)); > + } > + > if ((env->uncached_cpsr & CPSR_M) == mode) { > return env->regs[13]; > } else { > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 7bceb05..e69145d 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s, > * -- not a valid mode number > * -- a mode that's at a higher exception level > * -- Monitor, if we are Non-secure > - * For the UNPREDICTABLE cases we choose to UNDEF, except that for > - * "current mode is System" we will write a garbage SPSR. > - * (This is because we don't have access to our current mode here > - * and would have to do a runtime check to UNDEF for System.) > + * For the UNPREDICTABLE cases we choose to UNDEF. > */ > if (s->current_el == 1 && !s->ns) { > gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3); > @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s, > > addr = tcg_temp_new_i32(); > tmp = tcg_const_i32(mode); > + /* get_r13_banked() will raise an exception if called from System mode */ > + gen_set_condexec(s); > + gen_set_pc_im(s, s->pc - 4); > gen_helper_get_r13_banked(addr, cpu_env, tmp); > tcg_temp_free_i32(tmp); > switch (amode) { > @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s, > tcg_temp_free_i32(tmp); > } > tcg_temp_free_i32(addr); > + s->is_jmp = DISAS_UPDATE; > } > > static void disas_arm_insn(DisasContext *s, unsigned int insn)