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[46.188.121.154]) by smtp.gmail.com with ESMTPSA id h8sm4233679lfg.10.2016.02.29.11.24.46 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 29 Feb 2016 11:24:46 -0800 (PST) To: Peter Maydell , qemu-devel@nongnu.org References: <1456764438-30015-1-git-send-email-peter.maydell@linaro.org> From: Sergey Fedorov Message-ID: <56D49AFE.5060002@gmail.com> Date: Mon, 29 Feb 2016 22:24:46 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1456764438-30015-1-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c07::22e Cc: qemu-arm@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [PATCH] target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 3QucjyU/demF On 29.02.2016 19:47, Peter Maydell wrote: > In helper.c the expression > (env->uncached_cpsr & CPSR_M) != CPSR_USER > is always true; the right hand side was supposed to be ARM_CPU_MODE_USR > (an error in commit cb01d391). > > Since the incorrect expression was always true, this just meant that > commit cb01d391 had no effect. > > However simply changing the RHS here would reveal a logic error: if > the mode is USR we wish to completely ignore the attempt to set the > mode bits, which means that we must clear the CPSR_M bits from mask > to avoid the uncached_cpsr bits being updated at the end of the > function. > > Move the condition into the correct place in the code, fix its RHS > constant, and add a comment about the fact that we must be doing a > gdbstub write if we're in user mode. > > Fixes: https://bugs.launchpad.net/qemu/+bug/1550503 > Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov > --- > target-arm/helper.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 18c8296..935f13b 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -5490,9 +5490,16 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, > env->daif |= val & CPSR_AIF & mask; > > if (write_type != CPSRWriteRaw && > - (env->uncached_cpsr & CPSR_M) != CPSR_USER && > ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { > - if (bad_mode_switch(env, val & CPSR_M, write_type)) { > + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { > + /* Note that we can only get here in USR mode if this is a > + * gdb stub write; for this case we follow the architectural > + * behaviour for guest writes in USR mode of ignoring an attempt > + * to switch mode. (Those are caught by translate.c for writes > + * triggered by guest instructions.) > + */ > + mask &= ~CPSR_M; > + } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { > /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in > * v7, and has defined behaviour in v8: > * + leave CPSR.M untouched