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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	Patch Tracking <patches@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns
Date: Fri, 05 Feb 2016 16:17:57 +0000	[thread overview]
Message-ID: <87egcrnnbe.fsf@linaro.org> (raw)
In-Reply-To: <CAFEAcA_RJs_DaBa2YqP3z+-ykMntPULEWAYO8LnQz8Qzs+dyXA@mail.gmail.com>


Peter Maydell <peter.maydell@linaro.org> writes:

> On 5 February 2016 at 14:20, Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> Peter Maydell <peter.maydell@linaro.org> writes:
>>> -typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
>>> +typedef CPAccessResult CPAccessFn(CPUARMState *env,
>>> +                                  const ARMCPRegInfo *opaque,
>>> +                                  bool isread);
>>
>> I guess my only comment here is we've extended the call for every access
>> check with another parameter (and associated TCG activity) for something
>> only one handler currently cares about.
>>
>> Is there an argument for an rwaccessfn() that we use for just those
>> registers that care about the detail? I know system registers are hardly
>> a fast path priority but I'm concerned about knock on effects on
>> performance. Have you done any measurements?
>
> I haven't measured, no, but since there are only 3 arguments the
> third argument is going to be in a register on any host architecture
> we care about, which means the overhead is just going to be a single
> "load constant 0 or 1 into register before the call". I think that's
> going to be lost in the noise compared to actually having to make
> the function call at all, the work the function call does, and then
> the second function call later to do the read or write.

I was thinking of knock on effects on spilling other registers in the
TCG code. I guess this depends on how complex the code is around system
register access.

>
> thanks
> -- PMM


--
Alex Bennée

  reply	other threads:[~2016-02-05 16:17 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-03 13:38 [Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell
2016-02-03 13:38 ` [Qemu-arm] [PATCH 1/7] target-arm: Fix typo in comment in arm_is_secure_below_el3() Peter Maydell
2016-02-05  9:52   ` Alex Bennée
2016-02-06 11:49   ` Edgar E. Iglesias
2016-02-06 18:24   ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 2/7] target-arm: Implement MDCR_EL3 and SDCR Peter Maydell
2016-02-05 11:13   ` Alex Bennée
2016-02-05 11:28     ` Peter Maydell
2016-02-06 12:04   ` [Qemu-arm] " Edgar E. Iglesias
2016-02-06 18:42   ` [Qemu-arm] [Qemu-devel] " Sergey Fedorov
2016-02-08 13:11     ` Peter Maydell
2016-02-03 13:38 ` [Qemu-arm] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR Peter Maydell
2016-02-05 13:43   ` Alex Bennée
2016-02-06 12:17   ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 13:48     ` [Qemu-arm] " Peter Maydell
2016-02-06 16:03       ` Edgar E. Iglesias
2016-02-06 16:10   ` Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 4/7] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3 Peter Maydell
2016-02-05 14:09   ` Alex Bennée
2016-02-05 15:55     ` Peter Maydell
2016-02-06 18:43   ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns Peter Maydell
2016-02-05 14:20   ` Alex Bennée
2016-02-05 14:29     ` Peter Maydell
2016-02-05 16:17       ` Alex Bennée [this message]
2016-02-05 16:27         ` Peter Maydell
2016-02-05 16:43           ` Alex Bennée
2016-02-06 16:16   ` Edgar E. Iglesias
2016-02-06 18:52   ` [Qemu-arm] " Sergey Fedorov
2016-02-03 13:38 ` [Qemu-arm] [PATCH 6/7] target-arm: Implement NSACR trapping behaviour Peter Maydell
2016-02-05 16:07   ` Alex Bennée
2016-02-05 16:22     ` Peter Maydell
2016-02-06 16:42   ` Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 7/7] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57 Peter Maydell
2016-02-05 16:08   ` Alex Bennée
2016-02-06 16:43   ` [Qemu-arm] " Edgar E. Iglesias
2016-02-06 18:55   ` [Qemu-arm] [Qemu-devel] " Sergey Fedorov
2016-02-08 13:18 ` [Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell

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