From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y5sm4329196wrm.61.2021.04.29.03.30.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 03:30:13 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id ED4E91FF7E; Thu, 29 Apr 2021 11:30:12 +0100 (BST) References: <20210415163304.4120052-1-philmd@redhat.com> <20210415163304.4120052-2-philmd@redhat.com> User-agent: mu4e 1.5.12; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Laurent Vivier , Peter Maydell , Andrew Jones , =?utf-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Juan Quintela , Richard Henderson , Markus Armbruster , "Dr. David Alan Gilbert" , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , Thomas Huth , Igor Mammedov , qemu-devel@nongnu.org Subject: Re: [PATCH v4 01/12] MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section Date: Thu, 29 Apr 2021 11:30:08 +0100 In-reply-to: <20210415163304.4120052-2-philmd@redhat.com> Message-ID: <87pmydqt6z.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-TUID: lofrBq3feFYc Philippe Mathieu-Daud=C3=A9 writes: > We want the ARM maintainers and the qemu-arm@ list to be > notified when this file is modified. Add an entry to the > 'ARM TCG CPUs' section in the MAINTAINERS file. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 36055f14c59..d5df4ba7891 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -156,6 +156,7 @@ S: Maintained > F: target/arm/ > F: tests/tcg/arm/ > F: tests/tcg/aarch64/ > +F: tests/qtest/arm-cpu-features.c > F: hw/arm/ > F: hw/cpu/a*mpcore.c > F: include/hw/cpu/a*mpcore.h --=20 Alex Benn=C3=A9e