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Sat, 22 Aug 2026 14:06:42 -0700 (PDT) Received: from localhost ([2a02:8071:50c5:5c0::361b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2496296a46sm557817766b.21.2026.08.22.14.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Aug 2026 14:06:41 -0700 (PDT) From: Wadim Mueller To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Bin Meng , Paolo Bonzini , Fabiano Rosas Subject: Re: [RFC PATCH v2 00/14] hw/arm: add TI AM64x SoC and am64-virt machine In-Reply-To: <87qzjrojkl.fsf@draig.linaro.org> References: <20260820124824.618671-1-wafgo01@gmail.com> <87qzjrojkl.fsf@draig.linaro.org> Date: Sat, 22 Aug 2026 23:06:41 +0200 Message-ID: <87qzjpj25a.fsf@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=wafgo01@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 2026-08-21 11:26, Alex Benn=C3=A9e wrote: > Wadim Mueller writes: > >> Add support for the TI AM64x (Sitara AM6442) SoC and a board around it, >> ``am64-virt``. The model is complete enough to run the stock TI boot cha= in >> end to end: >> >> ROM boot (tiboot3.bin) -> R5 SPL -> TF-A/OP-TEE -> U-Boot -> Linux SMP >> >> This is a resend: I posted a first RFC back in May [1] but got no feedba= ck >> on it. Since then was the series rebased onto actual master, reworked for >> style and split into reviewable pieces, so I send it out again in the ho= pe >> of getting some review. >> >> RFC because I would like feedback on the overall approach before polishi= ng >> further; see the open questions at the end. >> >> [1] https://lore.kernel.org/qemu-devel/20260528211210.74266-1-wafgo01@gm= ail.com/ >> >> What is modelled >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > >> Open questions >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >> >> * pc-bios/dtb/am64-virt.dtb: patch 13 checks in a generated DTB (with >> its source) for convenience. I am not sure a machine-specific blob >> belongs in pc-bios; happy to drop it and have the functional test >> generate it with dtc instead, or drop the Linux-boot part of the tes= t. >> >> * Splitting the DMSC: hw/misc/ti-dmsc.c is large because TI-SCI is >> large. It could be split per message class (clocks / devices / >> processor boot / security) if reviewers prefer, at the cost of a >> non-functional intermediate state. >> >> * Only one of the four R5F cores is modelled. mc->max_cpus reserves >> room for the rest. Because the SoC realizes M4F/R5F vCPUs in addition >> to the A53s and every vCPU needs a TCG context slot inside >> smp.max_cpus, the machine defaults to the full vCPU budget. I would >> appreciate a better idea than the actual "fail early with an >> explanatory message" handling when the user passes a too-small -smp. >> >> * The register-level stubs (DDRSS in particular) fake success rather >> than modelling the hardware. That is deliberate, but tell me if you >> would rather see them as plain unimplemented-device windows plus >> firmware quirks elsewhere. > > I would add one more which is who is committing to maintain this model > if it is merged? > That would be me. The series already adds a MAINTAINERS entry with S: Maintained. In v3 I will make the F: patterns narrower, because hw/misc/ti-*.c currently claims every future TI misc device and not only the K3 ones. I develop and test firmware on real AM64x silicon (a phyCORE-AM64x SoM), and I use this model every day for this work, so I have both the hardware and the vendor boot chain here to reproduce regressions. I also intend to review patches which touch these files. The testing side of the same question I have answered in the thread of patch 14, where you raised it. Best regards, Wadim > --=20 > Alex Benn=C3=A9e > Virtualisation Tech Lead @ Linaro