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Fri, 21 Aug 2026 03:26:53 -0700 (PDT) Received: from draig.lan ([185.124.0.156]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2459222200sm374475566b.56.2026.08.21.03.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 03:26:52 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id E8AEE5F809; Fri, 21 Aug 2026 11:26:50 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Wadim Mueller Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Bin Meng , Paolo Bonzini , Fabiano Rosas Subject: Re: [RFC PATCH v2 00/14] hw/arm: add TI AM64x SoC and am64-virt machine In-Reply-To: <20260820124824.618671-1-wafgo01@gmail.com> (Wadim Mueller's message of "Thu, 20 Aug 2026 14:48:00 +0200") References: <20260820124824.618671-1-wafgo01@gmail.com> User-Agent: mu4e 1.14.3; emacs 30.1 Date: Fri, 21 Aug 2026 11:26:50 +0100 Message-ID: <87qzjrojkl.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Wadim Mueller writes: > Add support for the TI AM64x (Sitara AM6442) SoC and a board around it, > ``am64-virt``. The model is complete enough to run the stock TI boot chain > end to end: > > ROM boot (tiboot3.bin) -> R5 SPL -> TF-A/OP-TEE -> U-Boot -> Linux SMP > > This is a resend: I posted a first RFC back in May [1] but got no feedback > on it. Since then was the series rebased onto actual master, reworked for > style and split into reviewable pieces, so I send it out again in the hope > of getting some review. > > RFC because I would like feedback on the overall approach before polishing > further; see the open questions at the end. > > [1] https://lore.kernel.org/qemu-devel/20260528211210.74266-1-wafgo01@gma= il.com/ > > What is modelled > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Open questions > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > * pc-bios/dtb/am64-virt.dtb: patch 13 checks in a generated DTB (with > its source) for convenience. I am not sure a machine-specific blob > belongs in pc-bios; happy to drop it and have the functional test > generate it with dtc instead, or drop the Linux-boot part of the test. > > * Splitting the DMSC: hw/misc/ti-dmsc.c is large because TI-SCI is > large. It could be split per message class (clocks / devices / > processor boot / security) if reviewers prefer, at the cost of a > non-functional intermediate state. > > * Only one of the four R5F cores is modelled. mc->max_cpus reserves > room for the rest. Because the SoC realizes M4F/R5F vCPUs in addition > to the A53s and every vCPU needs a TCG context slot inside > smp.max_cpus, the machine defaults to the full vCPU budget. I would > appreciate a better idea than the actual "fail early with an > explanatory message" handling when the user passes a too-small -smp. > > * The register-level stubs (DDRSS in particular) fake success rather > than modelling the hardware. That is deliberate, but tell me if you > would rather see them as plain unimplemented-device windows plus > firmware quirks elsewhere. I would add one more which is who is committing to maintain this model if it is merged? --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro