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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH v2 2/3] fpu/softfloat: support ARM Alternative half-precision
In-reply-to: <9549d686-899d-7b3b-dae3-d3cc22528e50@linaro.org>
Date: Fri, 04 May 2018 13:26:09 +0100
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Richard Henderson <richard.henderson@linaro.org> writes:

> On 05/03/2018 11:17 AM, Peter Maydell wrote:
>> (target/i386 notably does not do this, we should check how
>> SSE and x87 handle NaNs in fp conversions first.)
>
> Hardware does silence NaNs.  I tested that earlier:
>
> https://lists.gnu.org/archive/html/qemu-devel/2018-04/msg03114.html

Does that include SSE? I know the hardware will silence NaN's if the
value is ever pushed into an x87 register (as GCC will do when
spilling/filling float).

>
>
> r~


--
Alex Benn=C3=A9e