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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id i21sm2712317pfd.219.2021.06.04.19.19.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Jun 2021 19:19:23 -0700 (PDT) Subject: Re: [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Claudio Fontana References: <20210604155312.15902-1-alex.bennee@linaro.org> <20210604155312.15902-52-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <8a3aa04e-917b-cfb2-124f-10a23062e81c@linaro.org> Date: Fri, 4 Jun 2021 19:19:21 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210604155312.15902-52-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TUID: Eu6b/KyE8RsJ On 6/4/21 8:52 AM, Alex Bennée wrote: > From: Claudio Fontana > > cpu-sysemu.c: > > we need this sysemu code for KVM too, so we move the code to > cpu-sysemu.c so we can reach a builable state. > > There will be further split later on in dedicated > exception modules for 32 and 64bit, after we make more > necessary changes to be able to split TARGET_AARCH64-only code. > > tcg/sysemu/tcg-cpu.c: > > the TCG-specific code we put in tcg/sysemu/, in preparation > for the addition of the tcg-cpu accel-cpu ARM subclass. > > Signed-off-by: Claudio Fontana > Signed-off-by: Alex Bennée > --- > target/arm/tcg/tcg-cpu.h | 31 ++ > target/arm/cpu-sysemu.c | 670 +++++++++++++++++++++++++++ > target/arm/tcg/helper.c | 734 ------------------------------ > target/arm/tcg/sysemu/tcg-cpu.c | 73 +++ > target/arm/tcg/sysemu/meson.build | 1 + > 5 files changed, 775 insertions(+), 734 deletions(-) > create mode 100644 target/arm/tcg/tcg-cpu.h > create mode 100644 target/arm/tcg/sysemu/tcg-cpu.c Reviewed-by: Richard Henderson r~