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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id 125sm12905580pfg.52.2021.06.14.12.39.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jun 2021 12:39:36 -0700 (PDT) Subject: Re: [PATCH v2 12/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210614151007.4545-1-peter.maydell@linaro.org> <20210614151007.4545-13-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <8d917c5a-0c50-927d-522c-9ae48db5926e@linaro.org> Date: Mon, 14 Jun 2021 12:39:34 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210614151007.4545-13-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.489, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: YSkxXjHtE3Vl On 6/14/21 8:09 AM, Peter Maydell wrote: > diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c > index c07110a145b..7282f56b18d 100644 > --- a/target/arm/mve_helper.c > +++ b/target/arm/mve_helper.c > @@ -168,5 +168,16 @@ DO_VSTR(vstrb, stb, 1, uint8_t) > DO_VSTR(vstrh, stw, 2, uint16_t) > DO_VSTR(vstrw, stl, 4, uint32_t) > > +DO_VLDR(vldrb_sh, ldsb, 2, int16_t) > +DO_VLDR(vldrb_sw, ldsb, 4, int32_t) > +DO_VLDR(vldrb_uh, ldub, 2, uint16_t) > +DO_VLDR(vldrb_uw, ldub, 4, uint32_t) > +DO_VLDR(vldrh_sw, ldsw, 4, int32_t) > +DO_VLDR(vldrh_uw, lduw, 4, uint32_t) > + > +DO_VSTR(vstrb_h, stb, 2, int16_t) > +DO_VSTR(vstrb_w, stb, 4, int32_t) > +DO_VSTR(vstrh_w, stw, 4, int32_t) Hmm, from the previous patch, > +#define DO_VLDR(OP, LDTYPE, ESIZE, TYPE) \ > + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ > + { \ > + TYPE *d = vd; \ > + uint16_t mask = mve_element_mask(env); \ > + unsigned b, e; \ > + /* \ > + * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ > + * beats so we don't care if we update part of the dest and \ > + * then take an exception. \ > + */ \ > + for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ > + if (mask & (1 << b)) { \ > + d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \ > + addr += ESIZE; \ > + } \ > + } \ > + mve_advance_vpt(env); \ > + } we are advancing ADDR by ESIZE, and not but the MSIZE of the memory access. Further, we're advancing ADDR under predication, whereas the increment should be unconditional (e * mbytes). r~