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Tue, 29 Jul 2025 09:00:59 -0700 (PDT) Received: from [192.168.0.102] ([187.75.37.236]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31e6625052asm12551264a91.6.2025.07.29.09.00.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Jul 2025 09:00:58 -0700 (PDT) Message-ID: <9209927c-6c5f-4499-a3ef-1f4c70951ad0@linaro.org> Date: Tue, 29 Jul 2025 13:01:50 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 46/82] target/arm: Implement FEAT_CHK To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org References: <20250727080254.83840-1-richard.henderson@linaro.org> <20250727080254.83840-47-richard.henderson@linaro.org> Content-Language: en-US From: Gustavo Romero In-Reply-To: <20250727080254.83840-47-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=gustavo.romero@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Richard, On 7/27/25 05:02, Richard Henderson wrote: > This feature contains only the CHKFEAT instruction. It has > no ID enable, being back-allocated into the hint nop space. > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 14 ++++++++++++++ > docs/system/arm/emulation.rst | 1 + > target/arm/tcg/a64.decode | 1 + > 3 files changed, 16 insertions(+) > > diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c > index 7831b3dab3..34d22cac8a 100644 > --- a/target/arm/tcg/translate-a64.c > +++ b/target/arm/tcg/translate-a64.c > @@ -2124,6 +2124,20 @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) > return true; > } > > +static bool trans_CHKFEAT(DisasContext *s, arg_CHKFEAT *a) > +{ > + uint64_t feat_en = 0; > + > + if (s->gcs_en) { > + feat_en |= 1 << 0; I understand that CHKFEAT is currently only tied to GCS but will cover more features in the future so we can keep feat_en |= 1 << 0 even if it could gate TCG andi directly on s->gcs_en and do andi with 0. ok. It's curious that this instruction is tied to x16, it seems easy to use any other general purpose register to query for the features. > + } > + if (feat_en) { > + TCGv_i64 x16 = cpu_reg(s, 16); > + tcg_gen_andi_i64(x16, x16, ~feat_en); > + } > + return true; > +} > + > static bool trans_CLREX(DisasContext *s, arg_CLREX *a) > { > tcg_gen_movi_i64(cpu_exclusive_addr, -1); > diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst > index 6ebf9c9ce9..b894aced89 100644 > --- a/docs/system/arm/emulation.rst > +++ b/docs/system/arm/emulation.rst > @@ -28,6 +28,7 @@ the following architecture extensions: > - FEAT_BF16 (AArch64 BFloat16 instructions) > - FEAT_BTI (Branch Target Identification) > - FEAT_CCIDX (Extended cache index) > +- FEAT_CHK (Check Feature Status) > - FEAT_CMOW (Control for cache maintenance permission) > - FEAT_CRC32 (CRC32 instructions) > - FEAT_Crypto (Cryptographic Extension) > diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode > index 8c798cde2b..4315ed8dab 100644 > --- a/target/arm/tcg/a64.decode > +++ b/target/arm/tcg/a64.decode > @@ -246,6 +246,7 @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB > AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 > AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 > AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 > + CHKFEAT 1101 0101 0000 0011 0010 0101 000 11111 > ] > # The canonical NOP has CRm == op2 == 0, but all of the space > # that isn't specifically allocated to an instruction must NOP Reviewed-by: Gustavo Romero Cheers, Gustavo