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X-Received-From: 2a00:1450:400c:c0c::22e Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 8/9] target/arm: Support some Thumb insns being always unconditional X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm , QEMU Developers , "patches@linaro.org" Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: AXGsycKJaIcM On 11 October 2017 at 03:52, Richard Henderson wrote: > On 10/09/2017 06:48 AM, Peter Maydell wrote: >> - if (dc->condexec_mask) { >> + if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { >> uint32_t cond = dc->condexec_cond; >> >> if (cond != 0x0e) { /* Skip conditional when condition is AL. */ > > Don't you still need to advance the condexec_mask? Yes -- that happens after we've called disas_thumb{,2}_insn() in thumb_tr_translate_insn(). This patch just makes always-unconditional insns behave as if the condition is AL. thanks -- PMM