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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-arm] [PATCH v2 09/11] target/arm: Decode aa64 armv8.3 fcmla
Date: Fri, 26 Jan 2018 10:07:14 +0000	[thread overview]
Message-ID: <CAFEAcA9PGHMPeATRHESeUEWaU17OpVw99p-+U9KzOPaitSgEGQ@mail.gmail.com> (raw)
In-Reply-To: <707306d7-8ee4-ab6b-2154-290647a72779@linaro.org>

On 26 January 2018 at 07:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 01/15/2018 10:18 AM, Peter Maydell wrote:
>>> +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
>>> +                         void *vfpst, uint32_t desc)
>>> +{
>>> +    uintptr_t opr_sz = simd_oprsz(desc);
>>> +    float16 *d = vd;
>>> +    float16 *n = vn;
>>> +    float16 *m = vm;
>>> +    float_status *fpst = vfpst;
>>> +    intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
>>> +    uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
>>> +    uint32_t neg_real = flip ^ neg_imag;
>>> +    uintptr_t i;
>>> +
>>> +    neg_real <<= 15;
>>> +    neg_imag <<= 15;
>>> +
>>> +    for (i = 0; i < opr_sz / 2; i += 2) {
>>> +        float16 e0 = n[H2(i + flip)];
>>> +        float16 e1 = m[H2(i + flip)] ^ neg_real;
>>> +        float16 e2 = e0;
>>> +        float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
>>
>> This is again rather confusing to compare against the pseudocode.
>> What order are your e0/e1/e2/e3 compared to the pseudocode's
>> element1/element2/element3/element4 ?
>
> The SVE pseudocode for the same operation is clearer than that in the main ARM
> ARM, and is nearer to what I used:
>
>   for e = 0 to elements-1
>     if ElemP[mask, e, esize] == '1' then
>         pair = e - (e MOD 2);  // index of first element in pair
>         addend = Elem[result, e, esize];
>         if IsEven(e) then  // real part
>             // realD = realA [+-] flip ? (imagN * imagM) : (realN * realM)
>             element1 = Elem[operand1, pair + flip, esize];
>             element2 = Elem[operand2, pair + flip, esize];
>             if neg_real then element2 = FPNeg(element2);
>         else  // imaginary part
>             // imagD = imagA [+-] flip ? (imagN * realM) : (realN * imagM)
>             element1 = Elem[operand1, pair + flip, esize];
>             element2 = Elem[operand2, pair + (1 - flip), esize];
>             if neg_imag then element2 = FPNeg(element2);
>         Elem[result, e, esize] = FPMulAdd(addend, element1, element2, FPCR);
>
> In my version, e0/e1 are element1/element2 (real) and e2/e3 are
> element1/element2 (imag).

Thanks. Could we use the same indexing (1/2/3/4) as the final Arm ARM
pseudocode?

thanks
-- PMM

  reply	other threads:[~2018-01-26 14:36 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-18 17:24 [Qemu-arm] [PATCH v2 00/11] ARM v8.1 simd + v8.3 complex insns Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 01/11] target/arm: Add ARM_FEATURE_V8_1_SIMD Richard Henderson
2018-01-15 17:21   ` [Qemu-arm] " Peter Maydell
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 02/11] target/arm: Decode aa64 armv8.1 scalar three same extra Richard Henderson
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 03/11] target/arm: Decode aa64 armv8.1 " Richard Henderson
2018-01-15 17:21   ` Peter Maydell
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 04/11] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element Richard Henderson
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 05/11] target/arm: Decode aa32 armv8.1 three same Richard Henderson
2018-01-15 17:37   ` Peter Maydell
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 06/11] target/arm: Decode aa32 armv8.1 two reg and a scalar Richard Henderson
2018-01-15 17:47   ` Peter Maydell
2018-01-26  7:18     ` [Qemu-devel] " Richard Henderson
2018-01-26 10:05       ` [Qemu-arm] " Peter Maydell
2018-01-26 13:41   ` Philippe Mathieu-Daudé
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 07/11] target/arm: Add ARM_FEATURE_V8_FCMA Richard Henderson
2018-01-15 17:53   ` Peter Maydell
2018-01-15 18:03     ` [Qemu-devel] " Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 08/11] target/arm: Decode aa64 armv8.3 fcadd Richard Henderson
2018-01-15 18:11   ` [Qemu-arm] " Peter Maydell
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 09/11] target/arm: Decode aa64 armv8.3 fcmla Richard Henderson
2018-01-15 18:18   ` [Qemu-devel] " Peter Maydell
2018-01-26  7:29     ` Richard Henderson
2018-01-26 10:07       ` Peter Maydell [this message]
2018-01-26 19:03         ` [Qemu-arm] " Richard Henderson
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 10/11] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
2018-01-15 18:46   ` Peter Maydell
2018-01-15 19:10     ` [Qemu-devel] " Richard Henderson
2018-01-15 18:49   ` [Qemu-arm] " Peter Maydell
2017-12-18 17:24 ` [Qemu-arm] [PATCH v2 11/11] target/arm: Decode aa32 armv8.3 2-reg-index Richard Henderson
2018-01-15 18:51   ` Peter Maydell

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