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Mon, 20 Oct 2025 07:15:05 -0700 (PDT) MIME-Version: 1.0 References: <20251014200718.422022-1-richard.henderson@linaro.org> <20251014200718.422022-26-richard.henderson@linaro.org> In-Reply-To: <20251014200718.422022-26-richard.henderson@linaro.org> From: Peter Maydell Date: Mon, 20 Oct 2025 15:14:53 +0100 X-Gm-Features: AS18NWBg0vW-Drd44P4O3CVZHAFPREI7HJsC4-iKjXZDQouJF9OhnH2H-rWnz_Q Message-ID: Subject: Re: [PATCH v2 25/37] target/arm: Extend TTBR system registers to 128-bit To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1132; envelope-from=peter.maydell@linaro.org; helo=mail-yw1-x1132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Tue, 14 Oct 2025 at 21:09, Richard Henderson wrote: > > So far, just extend the data type and check access; do not yet > consume the 128-bit table format. > > Signed-off-by: Richard Henderson > @@ -6196,9 +6244,12 @@ static const ARMCPRegInfo contextidr_el2 = { > static const ARMCPRegInfo vhe_reginfo[] = { > { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, > - .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, > - .raw_writefn = raw_write, > - .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, > + .type = ARM_CP_128BIT, > + .access = PL2_RW, .access128fn = access_d128, > + .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, > + .write128fn = vmsa_tcr_ttbr_el2_write128, .raw_write128fn = raw_write128, > + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]), > + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el_hi[2]) }, We set .fieldoffset twice -- one of these should be .fieldoffsethi. > #ifndef CONFIG_USER_ONLY > { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, > -- Otherwise Reviewed-by: Peter Maydell thanks -- PMM