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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id k5-v6si1397523qvg.278.2018.04.29.16.03.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 29 Apr 2018 16:03:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=i5j30r8o; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Received: from localhost ([::1]:57148 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fCvM5-0005PS-7Z for alex.bennee@linaro.org; Sun, 29 Apr 2018 19:03:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fCvLw-0005PF-MY for qemu-arm@nongnu.org; Sun, 29 Apr 2018 19:03:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fCvLv-0007qQ-Cs for qemu-arm@nongnu.org; Sun, 29 Apr 2018 19:03:32 -0400 Received: from mail-oi0-x230.google.com ([2607:f8b0:4003:c06::230]:40323) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fCvLv-0007q8-5h for qemu-arm@nongnu.org; Sun, 29 Apr 2018 19:03:31 -0400 Received: by mail-oi0-x230.google.com with SMTP id c203-v6so6042783oib.7 for ; Sun, 29 Apr 2018 16:03:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=9Ts9yWEL6HKT8pSr5XARfPFBwYJvo8rCD9KgI96cPro=; b=i5j30r8oBE0gVgy5lRxjhCl3I4dKPBHSgszqJG0Cho5rw9TagKNjr/dTPDN2xdYkWr EZoBM70rlXxtmO92KesJMgjdxoQIA5QEXeA2qgkP0z9at8Ikl65wAV9zJCErf01AxbsU W2PzsjZCUMUOSk/Cd39B7rczJ14Ab17wAgeMNtZhz6ntj7UmYx89fSc0kCaq5pqXwF8r wEcYRo+T4nSbQl1pYqUx0pa1mFjkgnnNxsL3S8maX9xam/enoyodaSErZZHGR3D3nMFW /PqfkGKL8O4ftPZzOnQ0gUCBPYwo1pN0cCKBciJTrnMad0D32w1844cXwZW1XpEe1VlW kdpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=9Ts9yWEL6HKT8pSr5XARfPFBwYJvo8rCD9KgI96cPro=; b=RnocLsDrgbCg+rw5dNvnsA/MMx+o6GXwmeqzLCDye/iauUR0Woii0alOo/ZZIPJACs BigM+S1KHBykT3Yp3mVRwhycTkiecD46dqnPbNPLhR2Qpoxgmpd+IB2jcFBhv6+0boft e3pDpZCkzjVak2y/u2oKK4DAIeYNRjYpI+GT4KGT6FXtqktDSHghST/N2ckabSgOaWtk yQf3ufxFfCcWEJC/Uod7Go/ke9Mkz4SkNPK249axbRSBXoUfwtxqUvy4LSrrQmSIILqR 5uTIEPjmaCW3T0ogcFVoLGpVsCy3Fqr1Z96bQ7OZSSRXyudmMdS1xC5g3dpAs2u4Fmvy 56xg== X-Gm-Message-State: ALQs6tBed+u1r1hJRTFB3wkmpcJTs8ZE7kOZTE+vFWwE5VI2dxEBu1py FH3Jz7Of7iMpeX/zfzyUM9i4HHH2iMbN6HSXIXNopQ== X-Received: by 2002:aca:170d:: with SMTP id j13-v6mr6478381oii.113.1525043010055; Sun, 29 Apr 2018 16:03:30 -0700 (PDT) MIME-Version: 1.0 Received: by 10.74.25.195 with HTTP; Sun, 29 Apr 2018 16:03:29 -0700 (PDT) In-Reply-To: <45076b60-a2d2-281a-3c85-6c21d87a49ff@linaro.org> References: <20180427002651.28356-1-richard.henderson@linaro.org> <20180427002651.28356-6-richard.henderson@linaro.org> <45076b60-a2d2-281a-3c85-6c21d87a49ff@linaro.org> From: Michael Clark Date: Mon, 30 Apr 2018 11:03:29 +1200 Message-ID: To: Richard Henderson Content-Type: multipart/alternative; boundary="000000000000e1c729056b04be3a" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::230 Subject: Re: [Qemu-arm] [PATCH 5/9] target/riscv: Use new atomic min/max expanders X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Emilio G. Cota" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , QEMU Developers , qemu-arm@nongnu.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: UvgZzsgf5U8e --000000000000e1c729056b04be3a Content-Type: text/plain; charset="UTF-8" On Sat, Apr 28, 2018 at 5:53 AM, Richard Henderson < richard.henderson@linaro.org> wrote: > On 04/26/2018 09:24 PM, Michael Clark wrote: > > > > > > On Fri, Apr 27, 2018 at 12:26 PM, Richard Henderson > > > > wrote: > > > > Cc: Michael Clark > > > Cc: Palmer Dabbelt > > > Cc: Sagar Karandikar > > > > Cc: Bastian Koppelmann > > > > Signed-off-by: Richard Henderson > > > > > > > > Reviewed-by: Michael Clark > > > > > If you give me a remote I can pull into my local workspace and test. The > change > > looks pretty straight-forward. There are tests for amos in riscv-tests > but no > > parallel tests (i.e. contended case). > > git://github.com/rth7680/qemu.git tgt-arm-atomic-2 I just did a fetch and only saw tgt-arm-atomic. Maybe you haven't pushed tgt-arm-atomic-2. In any case the tgt-arm-atomic branch passes riscv-tests. Michael. --000000000000e1c729056b04be3a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Sat, Apr 28, 2018 at 5:53 AM, Richard Henderson &l= t;richard= .henderson@linaro.org> wrote:
On 04/26/2018 09:24 PM, Michae= l Clark wrote:
>
>
> On Fri, Apr 27, 2018 at 12:26 PM, Richard Henderson
> <richard.hen= derson@linaro.org <mailto:richard.henderson@linaro.org>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0Cc: Michael Clark <mjc@sifive.com <mailto:mjc@si= five.com>>
>=C2=A0 =C2=A0 =C2=A0Cc: Palmer Dabbelt <palmer@sifive.com <mailto:palmer@sifive.com>>
>=C2=A0 =C2=A0 =C2=A0Cc: Sagar Karandikar <sagark@eecs.berkeley.edu
>=C2=A0 =C2=A0 =C2=A0<mailto:sagark@eecs.berkeley.edu>>
>=C2=A0 =C2=A0 =C2=A0Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de
>=C2=A0 =C2=A0 =C2=A0<mailto:kbastian@mail.uni-paderborn.de>>
>=C2=A0 =C2=A0 =C2=A0Signed-off-by: Richard Henderson <richard.henderson@linaro.org
>=C2=A0 =C2=A0 =C2=A0<mailto:richard.henderson@linaro.org>>
>
>
> Reviewed-by: Michael Clark <mjc@s= ifive.com <mailto:mjc@sifive.com>>
>
> If you give me a remote I can pull into my local workspace and test. T= he change
> looks pretty straight-forward. There are tests for amos in riscv-tests= but no
> parallel tests (i.e. contended case).

git://github.com/rth7680/qemu.git tgt-arm-atomic-2=

I just did a fetch and only saw=C2=A0tgt-a= rm-atomic. Maybe you haven't pushed tgt-arm-atomic-2.

In any case the=C2=A0tgt-arm-atomic branc= h passes riscv-tests.

Michael.
--000000000000e1c729056b04be3a--