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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2025 00:49:11.0975 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1aadb691-8e9d-4a47-9a7d-08de18e078c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6911 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=nicolinc@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Fri, Oct 31, 2025 at 10:49:52AM +0000, Shameer Kolothum wrote: > Just before the device gets attached to the SMMUv3, make sure QEMU SMMUv3 > features are compatible with the host SMMUv3. > > Not all fields in the host SMMUv3 IDR registers are meaningful for userspace. > Only the following fields can be used: > > - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF > - IDR1: SIDSIZE, SSIDSIZE > - IDR3: BBML, RIL > - IDR5: VAX, GRAN64K, GRAN16K, GRAN4K > > For now, the check is to make sure the features are in sync to enable > basic accelerated SMMUv3 support. Note that SSIDSIZE will be added in the follow-up PASID support. > Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index a2deda3c32..8b9f88dd8e 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -28,6 +28,98 @@ MemoryRegion root; > MemoryRegion sysmem; > static AddressSpace *shared_as_sysmem; > > +static bool > +smmuv3_accel_check_hw_compatible(SMMUv3State *s, Maybe rename to: SMMUv3State *smmu then... > + struct iommu_hw_info_arm_smmuv3 *info, > + Error **errp) > +{ > + /* QEMU SMMUv3 supports both linear and 2-level stream tables */ > + if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) != > + FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { this looks nicer: if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) != FIELD_EX32(smmu->idr[0], IDR0, STLEVEL)) { > +static bool > +smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > + Error **errp) > +{ > + struct iommu_hw_info_arm_smmuv3 info; > + uint32_t data_type; > + uint64_t caps; > + > + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data_type, > + &info, sizeof(info), &caps, errp)) { > + return false; > + } > + > + if (data_type != IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { > + error_setg(errp, "Wrong data type (%d) for Host SMMUv3 device info", > + data_type); > + return false; > + } > + > + if (!smmuv3_accel_check_hw_compatible(s, &info, errp)) { Nit: it doesn't seem to be necessary to have a wrapper? Nicolin