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Fri, 27 Mar 2026 07:54:58 -0700 (PDT) Received: from linaro.org ([2a10:d582:31e:0:66fe:5836:46c7:fd55]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919432f0sm16550151f8f.13.2026.03.27.07.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 07:54:58 -0700 (PDT) Date: Fri, 27 Mar 2026 14:54:57 +0000 From: Jim MacArthur To: Richard Henderson Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH RFC 2/2] tcg/aarch64/tcg-target.c.inc: Manual replace of I3310, I3313 Message-ID: References: <20260319-aarch64-tcg-instruction-format-rename-v1-0-8a13bf98f8ff@linaro.org> <20260319-aarch64-tcg-instruction-format-rename-v1-2-8a13bf98f8ff@linaro.org> <7be1406f-11ca-4422-bb3f-bc344d736ad7@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7be1406f-11ca-4422-bb3f-bc344d736ad7@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Fri, Mar 27, 2026 at 12:50:13PM +1000, Richard Henderson wrote: > On 3/19/26 22:12, Jim MacArthur wrote: > > These are not formats in themselves, but extra constants to OR in with > > the existing ldst_imm format. > > > > Signed-off-by: Jim MacArthur > > --- > > tcg/aarch64/tcg-target.c.inc | 64 +++++++++++++++++++++++++------------------- > > 1 file changed, 36 insertions(+), 28 deletions(-) > > > > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > > index e9f86176d2..1f59d40a77 100644 > > --- a/tcg/aarch64/tcg-target.c.inc > > +++ b/tcg/aarch64/tcg-target.c.inc > > @@ -458,8 +458,9 @@ typedef enum { > > Ildst_imm_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30, > > Ildst_imm_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30, > > - Ildst_imm_TO_I3310 = 0x00200800, > > - Ildst_imm_TO_I3313 = 0x01000000, > > + /* Additions to the ldst_imm format */ > > + ldst_imm_to_sign_extend = 0x00200800, > > "to sign extend" is wrong. > > C3.3.10 Load/store register (register offset) > > Perhaps ldst_imm_to_reg? > Quite right, ldst_imm_to_reg does make more sense. Thanks for checking. Jim