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From: Magnus Kulke <magnuskulke@linux.microsoft.com>
To: Aastha Rawat <aastharawat@linux.microsoft.com>
Cc: qemu-devel@nongnu.org, "Wei Liu" <wei.liu@kernel.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Daniel P. Berrangé" <berrange@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Anirudh Rayabharam" <anirudh@anirudhrb.com>,
	qemu-arm@nongnu.org, "Alexander Graf" <agraf@csgraf.de>,
	"Pedro Barbuda" <pbarbuda@microsoft.com>,
	"Mohamed Mediouni" <mohamed@unpredictable.fr>,
	"Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>,
	"Pierrick Bouvier" <pierrick.bouvier@oss.qualcomm.com>
Subject: Re: [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook
Date: Tue, 2 Jun 2026 15:24:35 +0200	[thread overview]
Message-ID: <ah7ZkxbmEMOgQw+5@example.com> (raw)
In-Reply-To: <20260527-mshv_accel_arm64_supp-v4-10-66d871dcdc53@linux.microsoft.com>

On Wed, May 27, 2026 at 05:00:46AM +0000, Aastha Rawat wrote:
> From: Magnus Kulke <magnuskulke@linux.microsoft.com>
> 
> In MSHV the hypervisor APIC is always used, so we to implement this hook
> to make sure the AP's vcpu thread is not blocked waiting for an INIT SIPI
> by the BSP. Without this change soft reboots with -smp cpus>=2 will
> hang.
> 
> Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
> ---
>  accel/mshv/mshv-all.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
> index 927e1b39bb..61a9d58546 100644
> --- a/accel/mshv/mshv-all.c
> +++ b/accel/mshv/mshv-all.c
> @@ -719,11 +719,23 @@ static const TypeInfo mshv_accel_type = {
>      .instance_size = sizeof(MshvState),
>  };
>  
> +/*
> + * Haulted vCPUs must still enter mshv_cpu_exec() so that MSHV_RUN_VP
> + * is called and the hypervisor can wake them (via SIPI on x86 or
> + * PSCI on ARM64).
> + */
> +
> +static bool mshv_vcpu_thread_is_idle(CPUState *cpu)
> +{
> +    return false;
> +}
> +
>  static void mshv_accel_ops_class_init(ObjectClass *oc, const void *data)
>  {
>      AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
>  
>      ops->create_vcpu_thread = mshv_start_vcpu_thread;
> +    ops->cpu_thread_is_idle = mshv_vcpu_thread_is_idle;
>      ops->synchronize_post_init = mshv_cpu_synchronize_post_init;
>      ops->synchronize_post_reset = mshv_cpu_synchronize_post_reset;
>      ops->synchronize_state = mshv_cpu_synchronize;
> 
> -- 
> 2.45.4

this has been merged independently since: dbfb680772d5184544f7c0a8bba96bec229c96e6

best,

magnus


  reply	other threads:[~2026-06-02 13:25 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-27  5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 01/15] accel/mshv: move msr.c to target/i386 Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 02/15] accel/mshv: extract common CPU register helpers Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 03/15] accel/mshv: add arch-specific accelerator init hook Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 04/15] meson, target/arm/mshv: Enable arm64 build & add initial MSHV support Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 05/15] target/arm/mshv: implement vcpu state operations for ARM64 Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 06/15] target/arm: convert host CPU feature ifdef ladder to runtime checks Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 07/15] target/arm/mshv: implement -cpu host for MSHV Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 08/15] accel/mshv: Add access_vp_regs synthetic proc features Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 09/15] target/arm: cpu: Mark MSHV supporting PSCI 1.3 Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook Aastha Rawat
2026-06-02 13:24   ` Magnus Kulke [this message]
2026-05-27  5:00 ` [PATCH v4 11/15] target/arm: extract MMIO emulation logic for HVF & WHPX Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 12/15] target/arm/mshv: add vCPU run loop Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 13/15] include/hw/hyperv: adjust hv_interrupt_control structure for arm64 Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 14/15] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation Aastha Rawat
2026-05-27  5:00 ` [PATCH v4 15/15] MAINTAINERS: updates for MSHV arm64 code Aastha Rawat

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