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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429eb4771cfsm5696426f8f.30.2025.11.06.07.44.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Nov 2025 07:44:25 -0800 (PST) Message-ID: Date: Thu, 6 Nov 2025 16:44:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 31/32] vfio: Synthesize vPASID capability to VM To: Shameer Kolothum , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-32-skolothumtho@nvidia.com> <1be3383e-843f-49b8-a246-59375c42aaae@redhat.com> From: Eric Auger In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: UxD8ReIXDkktGH-mmBP-PPdcpp2Yly8_bVZE4MsyXWs_1762443867 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.271, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 11/6/25 3:27 PM, Shameer Kolothum wrote: > >> -----Original Message----- >> From: Eric Auger >> Sent: 06 November 2025 13:56 >> To: Shameer Kolothum ; qemu- >> arm@nongnu.org; qemu-devel@nongnu.org >> Cc: peter.maydell@linaro.org; Jason Gunthorpe ; Nicolin >> Chen ; ddutile@redhat.com; berrange@redhat.com; >> Nathan Chen ; Matt Ochs ; >> smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >> zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; yi.l.liu@intel.com; >> Krishnakant Jaju >> Subject: Re: [PATCH v5 31/32] vfio: Synthesize vPASID capability to VM >> >> External email: Use caution opening links or attachments >> >> >> Hi Shameer, >> On 10/31/25 11:50 AM, Shameer Kolothum wrote: >>> From: Yi Liu >>> >>> If user wants to expose PASID capability in vIOMMU, then VFIO would also >> need to report? >>> report the PASID cap for this device if the underlying hardware supports >>> it as well. >>> >>> As a start, this chooses to put the vPASID cap in the last 8 bytes of the >>> vconfig space. This is a choice in the good hope of no conflict with any >>> existing cap or hidden registers. For the devices that has hidden registers, >>> user should figure out a proper offset for the vPASID cap. This may require >>> an option for user to config it. Here we leave it as a future extension. >>> There are more discussions on the mechanism of finding the proper offset. >>> >>> >> https://lore.kernel.org/kvm/BN9PR11MB5276318969A212AD0649C7BE8C >> BE2@BN9PR11MB5276.namprd11.prod.outlook.com/ >>> Since we add a check to ensure the vIOMMU supports PASID, only devices >>> under those vIOMMUs can synthesize the vPASID capability. This gives >>> users control over which devices expose vPASID. >>> >>> Signed-off-by: Yi Liu >>> Tested-by: Zhangfei Gao >>> Signed-off-by: Shameer Kolothum >>> --- >>> hw/vfio/pci.c | 37 +++++++++++++++++++++++++++++++++++++ >>> include/hw/iommu.h | 1 + >>> 2 files changed, 38 insertions(+) >>> >>> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c >>> index 06b06afc2b..2054eac897 100644 >>> --- a/hw/vfio/pci.c >>> +++ b/hw/vfio/pci.c >>> @@ -24,6 +24,7 @@ >>> #include >>> >>> #include "hw/hw.h" >>> +#include "hw/iommu.h" >>> #include "hw/pci/msi.h" >>> #include "hw/pci/msix.h" >>> #include "hw/pci/pci_bridge.h" >>> @@ -2500,7 +2501,12 @@ static int vfio_setup_rebar_ecap(VFIOPCIDevice >> *vdev, uint16_t pos) >>> static void vfio_add_ext_cap(VFIOPCIDevice *vdev) >>> { >>> + HostIOMMUDevice *hiod = vdev->vbasedev.hiod; >>> + HostIOMMUDeviceClass *hiodc = >> HOST_IOMMU_DEVICE_GET_CLASS(hiod); >>> PCIDevice *pdev = PCI_DEVICE(vdev); >>> + uint64_t max_pasid_log2 = 0; >>> + bool pasid_cap_added = false; >>> + uint64_t hw_caps; >>> uint32_t header; >>> uint16_t cap_id, next, size; >>> uint8_t cap_ver; >>> @@ -2578,12 +2584,43 @@ static void vfio_add_ext_cap(VFIOPCIDevice >> *vdev) >>> pcie_add_capability(pdev, cap_id, cap_ver, next, size); >>> } >>> break; >>> + case PCI_EXT_CAP_ID_PASID: >>> + pasid_cap_added = true; >>> + /* fallthrough */ >>> default: >>> pcie_add_capability(pdev, cap_id, cap_ver, next, size); >>> } >>> >>> } >>> >>> +#ifdef CONFIG_IOMMUFD >>> + /* >>> + * Although we check for PCI_EXT_CAP_ID_PASID above, the Linux VFIO >>> + * framework currently hides this capability. Try to retrieve it >>> + * through alternative kernel interfaces (e.g. IOMMUFD APIs). >> I don't catch this sentence . When are you supposed to read above >> PCI_EXT_CAP_ID_PASID cap id then? > That’s to make it future proof in case VFIO relaxes that. If that happens > the code above by default, will add the CAP and we may end with a > duplicate at below offset. OK thanks for the clarification. Then I would move the comment about VFIO kernel code currently hiding the extended cap along with + pasid_cap_added = true; and explain it is added to make it future proof in case VFIO relaxes that Eric > >>> + */ >>> + if (!pasid_cap_added && hiodc->get_cap) { >>> + hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_GENERIC_HW, >> &hw_caps, NULL); >>> + hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_MAX_PASID_LOG2, >>> + &max_pasid_log2, NULL); >>> + } >>> + >>> + /* >>> + * If supported, adds the PASID capability in the end of the PCIe config >>> + * space. TODO: Add option for enabling pasid at a safe offset. >>> + */ >>> + if (max_pasid_log2 && (pci_device_get_viommu_flags(pdev) & >>> + VIOMMU_FLAG_PASID_SUPPORTED)) { >>> + bool exec_perm = (hw_caps & IOMMU_HW_CAP_PCI_PASID_EXEC) ? >> true : false; >> can't you direct set exec_perm = (hw_caps & >> IOMMU_HW_CAP_PCI_PASID_EXEC); > True 😊 > > Thanks, > Shameer