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Mon, 04 Jul 2022 01:28:04 -0700 (PDT) Message-ID: Date: Mon, 4 Jul 2022 13:58:00 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220628042117.368549-1-richard.henderson@linaro.org> <20220628042117.368549-4-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: 3e5eoaYfRZtF On 7/1/22 16:36, Peter Maydell wrote: >> + /* >> + * The SME exception we are testing for is raised via >> + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called >> + * when EL1 is using A64 or EL2 using A64 and !TGE. >> + * See AArch32.CheckAdvSIMDOrFPEnabled(). >> + */ >> + if (el == 0 >> + && FIELD_EX64(env->svcr, SVCR, SM) >> + && (!arm_is_el2_enabled(env) >> + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) >> + && arm_el_is_aa64(env, 1) >> + && !sme_fa64(env, el)) { > > I can't get any of: > * the logic in the comment > * the logic in the C code > * the logic in the the pseudocode AArch32.CheckAdvSIMDOrFPEnabled() > which causes it to call AArch64.CheckFPEnabled() > to line up with each other. > > The comment has: > * (EL1 A64) OR (EL2 A64 && !TGE) > The pseudocode has: > * (!TGE && EL1 A64) OR (TGE && EL2 A64 && EL1 A64) > [seems odd that it is checking the width of EL1 in the TGE case > but I haven't followed the logic through to find out why] > The C code here has: > * (!TGE && EL2 A64 && EL1 A64) > > What am I missing ? I'm looking at 0487H.a... are you looking at a different version? Because the pseudocode I see isn't what you list above: > if PSTATE.EL == EL0 && (!EL2Enabled() || (!ELUsingAArch32(EL2) && HCR_EL2.TGE == '0')) && > !ELUsingAArch32(EL1) then So (!EL2 || (EL2 A64 && !TGE)) && EL1 A64 which is, as far as I can see, what the C code has. I'll adjust the comment, anyway. r~